Next gen in 2006?

[McFly]

http://money.cnn.com/2003/03/18/commentary/game_over/column_gaming/

Even the most optimistic sources don't expect to see the next "next generation" consoles until late 2004 – and that's almost certainly a fantasy. More and more, it appears that the PlayStation 3, Xbox 2 (or, as some are calling it, the "Ybox") and next Nintendo game machine won't see the light of day until 2006.

The consensus among game publishers is we're still a long way from seeing new consoles. Six months ago, the guess was 2005, but lately that estimate has been slipping forward.

"There's always a question I get: 'Will Microsoft try to beat Sony to the punch?'," said Gysi. "Quite frankly, we hear conflicting things. Microsoft told us a few months ago that they would probably not try and beat Sony and [would] launch, more or less, at the same time as the PlayStation 3."

If nothing's said at E3, the industry's annual trade show in May, 2006 becomes a much safer, if not certain, bet, say analysts.

One year more to hype the next gen machines.

Fredi

 

[nonamer]

I've been thinking this for a while now. For a console to truely be "next-gen," the main components will have to be on a 65nm process, which I think only a few(Intel, really) will have it by the second half of 2005. Even if others manage to have it by 2005, they would still need more time to ramp up production and it will be a while before you would have enough for a launch. 2005 would really be pushing it as a launch period. My guess is this: Small PS3 launch in Japan in late-2005 at the earliest, the "real" launches all occur in mid to late 2006.

 

[Tahir2]

'the main components will have to be on 65nm'

Why? Didn't some company just prove that you do not rely on process technology alone? :? In fact didn't another company just prove that overly relying on process technology is a bad idea?

 

[McFly]

Looks like Sony really will have 65nm ready in 2004:

Toshiba, Sony take trench capacitors to 90-nm node

By Yoshiko Hara
EE Times
January 17, 2003 (12:48 p.m. EST)


Archives
TOKYO — Toshiba Corp. said it is leveraging its deep-trench-capacitor DRAM structure, which it has championed as a process driver since the 0.25-micron generation, to migrate its system-on-chip devices to the 90-nanometer and 65-nm process nodes ahead of its competitors.

Process development partner Sony Corp., meanwhile, is formulating plans for production at the two next-generation nodes and said it will migrate to the trench-capacitor structure from a stacked-capacitor architecture developed with Fujitsu.

Toshiba has been shipping engineering samples of 90-nm embedded-DRAM devices since November and expects to begin volume production in March with a startup capacity of 1 million units per month. Small-scale production of devices at the 65-nm node is expected a year later, in March 2004.

The processes have been in development under a three-year joint R&D project launched with Sony in April 2001. Engineers from both companies have been working at Toshiba's research center in Shinsugita, Yokohama, near Tokyo.

Strange bedfellows

Sitting next to a competitor's engineers to discuss technology development and R&D cost sharing has been "quite a new experience for Toshiba engineers," said Tatsuo Noguchi, senior manager of the advanced CMOS technology group at Toshiba Semiconductor Co.

"Sony has been working with partners since the 0.18 micron generation. For 90 and 65 nm, we collaborated with Toshiba," said Naoaki Nagashima, general manager of the integration technology department at Sony Semiconductor Network Co.

Total investment by the two companies is expected to be about 15 billion yen (about $127 million) for the three-year project. The first phase, targeting the 90nm-node, was completed in September. Toshiba immediately began risk (test) production at its Oita fab.

Work on the 65-nm process started last April and is scheduled for completion by March 2004. Toshiba intends to begin 65-nm production immediately upon completion of the joint R&D work. A 300-mm fab to be built at the Oita site is slated to begin turning out devices in the 65-nm process next year.

Sony has made no firm decisions on when and where to begin production of devices using the CMOS4 and CMOS5 (90- and 65-nm) processes, according to Nagashima. One decision that has been made however, is that Sony will adopt the processes jointly developed with Toshiba and will switch to deep-trench-type DRAM for its embedded-DRAM devices, dropping the stacked-capacitor structure co-developed with Fujitsu.

"Toshiba's Oita fab is ready for volume production of CMOS4 process devices, which we believe [puts us in the lead at the 90-nm node]," said Masaka-zu Kakumu, general manager of Toshiba Semi's advanced logic technology department.

The company attributes its advantage in embedded-DRAM devices to the deep-trench capacitor. When trench-capacitor DRAMs are integrated onto system-on-chip devices, the DRAM process is completed before the logic device process. In stacked-capacitor-structure embedded DRAM, by contrast, the DRAM cell is built on the metal wiring layer, and the high-temperature process used for the DRAM cells can deteriorate the transistors underneath that layer, Toshiba claims.

The CMOS4 and CMOS5 processes continue a practice Toshiba has had in place since the 0.25-micron generation, when trench-capacitor DRAM became the linchpin technology for process advances at the company. According to Toshiba, the strategy has given it a leg up at the 130-nm node, where it claims to be the only company to date to have undertaken true mass production of embedded DRAM. For its 90-nm process, device yields for 32-Mbit embedded DRAM have reached the volume-production level, according to Kakumu.

At Toshiba America, sales are under way for the TC300 family, based on the CMOS4. The devices feature up to 11 layers of copper metal interconnect with low-k dielectric and logic densities of up to 400,000 gates/mm2.

For the 90-nm node, Artisan Components will provide libraries for Toshiba's devices, with availability expected this summer. Toshiba offers proprietary libraries but expects Artisan's CMOS4 environment to appeal to customers of foundries, such as Taiwan Semiconductor Manufacturing Co., to which Artisan will provide its design platform and libraries. Foundry customers can move to Toshiba's process using the design interface provided by Artisan.

Toshiba added ArF lithography and low-k dielectric facilities to the clean room of its Oita fab for CMOS4 fabrication. The CMOS4 line now has an 8-inch wafer capacity of 27,500 a month. Toshiba and Oita TS Semiconductor Co. Ltd. (OT-SS), a joint-venture fab with Sony Computer Entertainment Inc., share the fab's capacity.

CMOS5

Sony and Toshiba presented the basic technologies for their 65-nm process in December at the International Electron Devices Meeting. "We have reached a level where we can show the performance of the transistor fabricated on the process. On this level, we are sure that we can begin production in March 2004," said Seiji Yamada, chief specialist at Toshiba Semi's advanced CMOS technology group.

Fabricated with 193-nm lithography and phase-shift masks, the transistor is reported to hit switching speeds of 0.72 picosecond for an n-MOSFET and 1.41 ps for a p-MOSFET at 0.85 volt. The embedded DRAM cell measures 0.11 micron2, allowing a 256-Mbit DRAM to be housed on-chip with logic. The process' embedded SRAM has a cell size of 0.6 micron2.

The new technology enables a 180-nm pitch, a 75 percent shrink from the 90-nm generation. The process employs a low-k dielectric material with a targeted effective interlayer dielectric constant of around 2.7.

Toshiba intends to prepare up to 13 usable metal layers for CMOS5 to provide design leeway for customers seeking to use existing IP with multiple layers on the 65-nm platform.

Sony & Toshiba really ahead of the rest? Looks like we will see early PS3 chips mid 2004.

Fredi

 

[jvd]

Looks like Sony really will have 65nm ready in 2004:


Sony & Toshiba really ahead of the rest? Looks like we will see early PS3 chips mid 2004.

Fredi

I don't think they are ahead of the rest. I think they just really need this more than intel does. I'm sure intel can sink the same amount of money into .65nm but they don't need to cause amd can't afford it. So really sony and toshiba need to have the chip on .65nm to reach thier goals. I'm sure the chip will be way to big and way to expensive and will run way to hot on .9nm. Sure they can do it. But at they will only ship however many they need to at .9nm if problems on .65nm happen. I figure if they have to make it at .9nm for whatever reason it will slip lower clocked and with less on die ram and of course all the future ones on .65nm will be made the same way.

I wonder if we will see the ps2 chips drop to .65nm and see a pstwo put out

 

[nonamer]

Looks like Sony really will have 65nm ready in 2004:

<SNIP>

Sony & Toshiba really ahead of the rest? Looks like we will see early PS3 chips mid 2004.

Fredi

That's just for DRAM production. AFAIK, a real fab with 300mm wafers cost like 2.5 billion for 90nm, and billions more for 65nm, so their not investing enough in this to produce actual chips with that.

 

[Dural]

That's just for DRAM production. AFAIK, a real fab with 300mm wafers cost like 2.5 billion for 90nm, and billions more for 65nm, so their not investing enough in this to produce actual chips with that.

That is what I was thinking after reading the thread zidane1strife posted. The article above says Toshiba and Sony are only investing $127 million for the three year project which is way less than how much it said it costs in the other thread.

Building a 300-mm, 90-nanometer fab is expected to cost a whopping $4 billion

 

[Vince]

That is what I was thinking after reading the thread zidane1strife posted. The article above says Toshiba and Sony are only investing $127 million for the three year project which is way less than how much it said it costs in the other thread.

That $127M USD is just for the R&D aspects conducted in the joint SCE-Toshiba project (eg. developing the process).

Toshiba isn't building an entirely new Fab for production at 65nm, but rather is building 65nm lines at the existing Oita Fab or, perhaps, building concurrently. I'm really not informed of the foundry agreements and what the entail at this point - but it's one of the above. They [Toshiba] have also asked Sony to help with the associated costs of new foundry/lines.

Conventional wisdom dating from 2001 stated that IBM's brand-new bleeding-edge 300mm Fab at Fishkill, NY would be used for Cell-based production. Or atleast IBM said so then.


Also, AFAIK - the above is describing their eDRAM production, not strait-up DRAM. The diffrence, AFAIK, is that CMOS5 can be integrated together with logic and this has diffrent timings, control, et al. Correct me if I'm wrong - hell, I'd like to learn more about this. Mfa?

 

[Panajev2001a]

From an earlier ( same month ) PR:

The new SoC technologies for 65nm process generation include: 1) a high-performance transistor with the world's fastest switching speed; 2) the world's smallest cell for embedded DRAM; and 3) the world's smallest cell for embedded SRAM.

 

[ToxicTaZ]

HD PS3 Anniversary System (10 Years) of PlayStation!

Sony will show the HD PS3 at TOKYO GAME SHOW 2004! (Japan)
http://tgs.cesa.or.jp/english/index.html
Sony HD PS3 launched & delivered in Japan by Christmas of 2004!

Sony will show the PS3 at The Electronic Entertainment Expo (E3) 2005!
http://www.e3expo.com/
Sony HD PS3 launch in the U.S. some time in September 2005!

And Sony HD PS3 launched in Europe by Christmas of 2005!

So NOT in 2006! SORRY!

The Sony HD PS3 is the PlayStation Anniversary System (10 Years)!
thx

 

[nonamer]

That is what I was thinking after reading the thread zidane1strife posted. The article above says Toshiba and Sony are only investing $127 million for the three year project which is way less than how much it said it costs in the other thread.

That $127M USD is just for the R&D aspects conducted in the joint SCE-Toshiba project (eg. developing the process).

Toshiba isn't building an entirely new Fab for production at 65nm, but rather is building 65nm lines at the existing Oita Fab or, perhaps, building concurrently. I'm really not informed of the foundry agreements and what the entail at this point - but it's one of the above. They [Toshiba] have also asked Sony to help with the associated costs of new foundry/lines.

Conventional wisdom dating from 2001 stated that IBM's brand-new bleeding-edge 300mm Fab at Fishkill, NY would be used for Cell-based production. Or atleast IBM said so then.


Also, AFAIK - the above is describing their eDRAM production, not strait-up DRAM. The diffrence, AFAIK, is that CMOS5 can be integrated together with logic and this has diffrent timings, control, et al. Correct me if I'm wrong - hell, I'd like to learn more about this. Mfa?

A $127 million upgrade would not be much of an upgrade at all. AFAIK, the move from 90nm to 65nm requires the abandoning of lenses for mirrors, and the production process will have to done in a vacuum. You can't just "upgrade" you way around huge roadblocks like these.

For those who think 65nm will be in 2004:
Get real. Companies like IBM, Intel (especially Intel), etc., spend billions upon billions every year in fabrication technology. If Toshiba could get it in 2004, the before mentioned companies could do so too. The fact that they can't signifies a lot.

 

[marconelly!]

A $127 million upgrade would not be much of an upgrade at all.

He said it's for R&D, not the upgrades, no?

 

[Vince]

He said it's for R&D, not the upgrades, no?

Yeah, word on the street is that reading the post helps... but then again, I doubt he cares.

For those who think 65nm will be in 2004:
Get real. Companies like IBM, Intel (especially Intel), etc., spend billions upon billions every year in fabrication technology. If Toshiba could get it in 2004, the before mentioned companies could do so too. The fact that they can't signifies a lot.

I think you shouldn't talk my friend; when forced to choose between a Toshiba exec whose company is collaberating with IBM and Sony - and you... I think the choice is obvious.

Besides, If you has any idea what you're talking about you'd know that Intel has 65nm production slated by 2005 aswell.

What we're concerning ourselves with are the founderies such as TSMC, or UMC who, forward looking, are limited due to capital investment. This only compounds the lithography gap of ~6months that already exists.

It's in these conditions (eg. Founderies) where the major 3D players fabricate their chips and will be the limiting portion of the NGConsoles design. Intel might have 65nm ready at a comperable time as the Toshiba-IBM-Sony trio, but it's irrelevent as they will use it for their major ASIC production which, like the current Pentium or as their histrory shows, hardly pushes the available lithography process like Sony-Toshiba-IBM can with their dedicated IC.

Thus, according to conventional logic (which has the possibility to be wong this generation if MS gets what they ask for); while Intel may have the Lith. process it's irrelevent in that case and where it's needed (eg. TSMC/UMC), it's not there.

 

[mr]

Vince, your last post summs up the current outlook of lithography (as we know it) quite nicely IMO.
You might want to save it.

 

[nonamer]

Vince: I said 2004 would be impossible, not 2005, though I agree with the statement that foundries will get it even later.