MIPS Series5 Now Official

Discussion in 'Mobile Graphics Architectures and IP' started by iwod, Jun 26, 2013.

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  1. Ailuros

    Ailuros Epsilon plus three
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    *faints* :lol:
     
  2. alexvoica

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    Re: Your question on Anandtech, configuration is not the word I should have used (it implies hardware). It is dynamic, yet.
     
  3. Exophase

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    Thanks, and welcome to the forums. For those confused, this is in response to a question I made in the comments on the AT article:

    Your response does make things clearer, but I'm still left wondering a bit how the modes work. When you say dynamic, does this mean a software driven state or a hardware driven state? Software driven would mean that it's in one instruction per cycle per thread mode so long as both virtual cores are set as active. Dynamic would mean that it switches on fine grained stall events like cache misses. A fixed scheme will work great on benchmarks like Dhrystone and Coremark that virtually never miss in L1 cache. But the benefit would be smaller in real world apps that do spend a significant amount of time in memory stalls.
     
  4. mboeller

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    well "fatter" IMHO no... but at least OoO, albeit still 32bit:

    http://www.imgtec.com/mips/warrior/pclass.asp

     
  5. alexvoica

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    I don't know if you've noticed but your question has already been answered.
    http://anandtech.com/comments/8457/mips-strikes-back-64bit-warrior-i6400-architecture-arrives/419569

    The main purpose of SMT is to keep the CPU busy(/-ier), remove idle states and deliver sustained/better performance. This feature maps very well to how Linux-based operating systems handle multithreading, offering improved QoS. Beyond that, I can't/shouldn't comment any further.
     
  6. alexvoica

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    I tried to reply to your post but a moderator must first approve it.
     
  7. mboeller

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    link from Ailuros:

    http://techent.tv/mips-i6400-just-another-64-bit-architecture-android/

    that is really fast!
     
  8. tangey

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    I suspect that that quote should be " end of next year" ?
     
  9. Ailuros

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    Under normal conditions I'd say you're most likely right, however:


    http://www.imgtec.com/news/detail.asp?ID=923

    If there's something wrong in IMG's own announcement, no wonder the author got it wrong too.

    Seeing also how "soon" 6XT GPU IP ended up in Apple A8 there's no other explanation for me at this point: IMG simply announces new IP quite a long time after its first IP availability, otherwise they wouldn't had secured multiple licenses already for the I6400 on the day of announcement. How long before is a good question of course.
     
  10. tangey

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    Well I saw that at the time, and read it to mean that lead partners have access to the IP now, and that it will be generally available for licensing in Dec 2014.

    AFAIK, IMG habitually don't talk about availability of CHIPS, when doing IP announcements, let alone devices containing chips containing their IP.
     
    #30 tangey, Sep 25, 2014
    Last edited by a moderator: Sep 25, 2014
  11. alexvoica

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    The author of that article has confused general availability of the IP (which is December 2014) with the timeframe when products will be available (12-18 months after general availability).
     
  12. tangey

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    Thanks for confirming.
     
  13. Ailuros

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    Now it's clear of course. I should have known better.

    ---------------------------------------

    Thanks Alex for the clarification.
     
  14. Tabris

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  15. Laurent06

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    My understanding is that they are not replacing the Xeon, but the on-chip controller (which is an ARM926 on PEZY-SC).
     
  16. Tabris

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    http://eetimes.jp/ee/articles/1511/17/news060.html
    this interview said that both ARM926 and the host CPU Intel Xeon will be repleace by the MIPS core inside the chip.
     
  17. Laurent06

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    That definitely looks much more interesting then! Booting X86 away always is good news :D
     
  18. tangey

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    roninja likes this.
  19. Tabris

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    maybe OT,
    Pezy-SC2 use threir own UltraMemory 3D-stacked DRAM which have 500GB/s bandwidth per chip, 4TB/s in total.
    UltraMemory team was lead by former CTO of Elipida.
     
  20. Tabris

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    http://news.mynavi.jp/articles/2016/04/25/pezy/

    more info about Pezy-SC2:
    process: TSMC 16nm FinFET
    engineering sample: Feb 2017
    config: 4096 Pezy-SC logic cores + 12 MIPS64 Warrior cores
    Processing Power @1GHz: 8.2TFlops(Double Precision)
    DRAM Interface: TCI (Max 32GB) + DDR4(Max 256GB)
    Bandwidth @1GHz: 4.1TB/s
     
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