MIPS Series5 Now Official

[Ailuros]

That would probably be the unannounced Rys SKU

*faints*

 

[alexvoica]

Re: Your question on Anandtech, configuration is not the word I should have used (it implies hardware). It is dynamic, yet.

 

[Exophase]

Re: Your question on Anandtech, configuration is not the word I should have used (it implies hardware). It is dynamic, yet.

Thanks, and welcome to the forums. For those confused, this is in response to a question I made in the comments on the AT article:

It behaves like a superscalar CPU when used in a single threaded configuration and like an in-order design in multithreading variants.

Hi Alex, could you clarify what you mean by this comment? Superscalar and in-order are completely orthogonal properties, and I would expect that it always behaves like an in-order design regardless of SMT. Do you mean that in SMT mode it can only dispatch one instruction per cycle from the same thread? If that's the case, surely this is something that can be dynamically configured based on active thread count and not a fixed property of the processor?

Your response does make things clearer, but I'm still left wondering a bit how the modes work. When you say dynamic, does this mean a software driven state or a hardware driven state? Software driven would mean that it's in one instruction per cycle per thread mode so long as both virtual cores are set as active. Dynamic would mean that it switches on fine grained stall events like cache misses. A fixed scheme will work great on benchmarks like Dhrystone and Coremark that virtually never miss in L1 cache. But the benefit would be smaller in real world apps that do spend a significant amount of time in memory stalls.

 

[mboeller]

Are there plans for fatter cores? Dual issue in-order seems a little unambitious even for mobile or low power server segments.

Cheers

well "fatter" IMHO no... but at least OoO, albeit still 32bit:

http://www.imgtec.com/mips/warrior/pclass.asp

- High-performance, 16-stage, wide issue, out-of-order (OoO) pipeline
- Quad instruction fetch per cycle
- Triple bonded dispatch per cycle
- Instruction peak issue of 4 integer and 2 SIMD operations per cycle
- Sophisticated branch prediction scheme, plus L0/L1/L2 branch target buffers (BTBs), Return Prediction Stack (RPS), Jump Register Cache (JRC)
- Instruction bonding – merges two 32-bit integer accesses into one 64-bit access, or two 64-bit floating point accesses into one 128-bit access for up to 2x increase on memory-intensive data movement routines

 

[alexvoica]

Your response does make things clearer, but I'm still left wondering a bit how the modes work. When you say dynamic, does this mean a software driven state or a hardware driven state?

I don't know if you've noticed but your question has already been answered.
http://anandtech.com/comments/8457/mips-strikes-back-64bit-warrior-i6400-architecture-arrives/419569

The main purpose of SMT is to keep the CPU busy(/-ier), remove idle states and deliver sustained/better performance. This feature maps very well to how Linux-based operating systems handle multithreading, offering improved QoS. Beyond that, I can't/shouldn't comment any further.

 

[alexvoica]

I tried to reply to your post but a moderator must first approve it.

 

[mboeller]

link from Ailuros:

http://techent.tv/mips-i6400-just-another-64-bit-architecture-android/

They also mentioned that the earliest we will see a I6400 powered device will be at the end of this year. So it looks like there is a new player in the block and by the looks of it, it is going to be a very interesting year for Android next year on.

that is really fast!

 

[tangey]

I suspect that that quote should be " end of next year" ?

 

[Ailuros]

I suspect that that quote should be " end of next year" ?

Under normal conditions I'd say you're most likely right, however:


http://www.imgtec.com/news/detail.asp?ID=923

Unsurprisingly, we’ve already secured licensees for the I6400 across multiple markets.

Imagination is already engaged with multiple lead I6400 licensing partners, with general availability scheduled for December 2014.

If there's something wrong in IMG's own announcement, no wonder the author got it wrong too.

Seeing also how "soon" 6XT GPU IP ended up in Apple A8 there's no other explanation for me at this point: IMG simply announces new IP quite a long time after its first IP availability, otherwise they wouldn't had secured multiple licenses already for the I6400 on the day of announcement. How long before is a good question of course.

 

[tangey]

Imagination is already engaged with multiple lead I6400 licensing partners, with general availability scheduled for December 2014.

Well I saw that at the time, and read it to mean that lead partners have access to the IP now, and that it will be generally available for licensing in Dec 2014.

AFAIK, IMG habitually don't talk about availability of CHIPS, when doing IP announcements, let alone devices containing chips containing their IP.

 

[alexvoica]

I suspect that that quote should be " end of next year" ?

The author of that article has confused general availability of the IP (which is December 2014) with the timeframe when products will be available (12-18 months after general availability).

 

[tangey]

The author of that article has confused general availability of the IP (which is December 2014) with the timeframe when products will be available (12-18 months after general availability).

Thanks for confirming.

 

[Ailuros]

Well I saw that at the time, and read it to mean that lead partners have access to the IP now, and that it will be generally available for licensing in Dec 2014.

AFAIK, IMG habitually don't talk about availability of CHIPS, when doing IP announcements, let alone devices containing chips containing their IP.

Now it's clear of course. I should have known better.

---------------------------------------

Thanks Alex for the clarification.

 

[Tabris]

PEZY Computing just announced that they will replace the Intel Xeon E5v3 with 64bit MIPS Warrior for PEZY-SC2, successor of many-core accelerator PEZY-SC, which powered the top 3 of Green500 June 2015.


http://blog.imgtec.com/mips-processors/pezy-licenses-mips-for-green-supercomputing

Japanese
http://www.pezy.co.jp/news/PEZY_PR_20151116.pdf
http://techon.nikkeibp.co.jp/atcl/news/15/111601181/

 

[Laurent06]

PEZY Computing just announced that they will replace the Intel Xeon E5v3 with 64bit MIPS Warrior for PEZY-SC2, successor of many-core accelerator PEZY-SC, which powered the top 3 of Green500 June 2015.

My understanding is that they are not replacing the Xeon, but the on-chip controller (which is an ARM926 on PEZY-SC).

 

[Tabris]

My understanding is that they are not replacing the Xeon, but the on-chip controller (which is an ARM926 on PEZY-SC).

http://eetimes.jp/ee/articles/1511/17/news060.html
this interview said that both ARM926 and the host CPU Intel Xeon will be repleace by the MIPS core inside the chip.

 

[Laurent06]

http://eetimes.jp/ee/articles/1511/17/news060.html
this interview said that both ARM926 and the host CPU Intel Xeon will be repleace by the MIPS core inside the chip.

That definitely looks much more interesting then! Booting X86 away always is good news

 

[tangey]

IMG just announced a new high-end MIPS64 CPU IP, already licensed for a HPC application. the warrior P6600
http://imgtec.com/mips/warrior/p-class-p6600-multiprocessor-core/

Given PEZY announcement yesterday (which did not specify a particular MIPS64 IP), Looks odds on that PEZY is the licenses for warrior P6600

 

[Tabris]

maybe OT,
Pezy-SC2 use threir own UltraMemory 3D-stacked DRAM which have 500GB/s bandwidth per chip, 4TB/s in total.
UltraMemory team was lead by former CTO of Elipida.

 

[Tabris]

http://news.mynavi.jp/articles/2016/04/25/pezy/

more info about Pezy-SC2:
process: TSMC 16nm FinFET
engineering sample: Feb 2017
config: 4096 Pezy-SC logic cores + 12 MIPS64 Warrior cores
Processing Power @1GHz: 8.2TFlops(Double Precision)
DRAM Interface: TCI (Max 32GB) + DDR4(Max 256GB)
Bandwidth @1GHz: 4.1TB/s