March 31 Cell thread

[glw]

Even if the BE did hit a Tflop/s most supercomputer
users require decent memory capacity and bandwidth.

The ratio of bandwidth (external) to floating point
performance for the BE is likely to be very low. This
would limit it's application to very few problems.
Graphics with high locality and a very repetitive nature
is one of the few applications where an architecture
like the BE might shine, it's not surprising the most
novel architectures tend to pick graphics and media
applications as examples of their prowess.

People need to get away from looking at the BE as a
general purpose computer and realise that the design
will likely be closer to contemporary GPUs. i.e. NV50/60
and the R500/R600. The actual PPC CPUs will spend
most of their time keeping the APUs busy and handling
those tasks which aren't suitable for stream processing.

 

[Megadrive1988]

IBM, Sony, and Toshiba are working on a Power chip derivative called Cell, which is thought to have many streamlined cores, as the basis of future electronics devices. Sony announced two months ago it had greased IBM's palm with $325m to work out the kinks in the 65 nanometer processes it will use to create Cell.

http://www.cbronline.com/currentnews/77ac2f2cc1fb734880256e690038578e

 

[Megadrive1988]

btw David, I very much like the idea of an MCM Broadband Engine.

actually my imagination likes to go further. it would be 'so neato' if Broadband Engines themselves could be combined together to form MCMs.

IIRC, the Sony patent mentions upto 5 Broadband Engines can be linked via optical cable, in massive systems. I suppose that rules out PS3 being one of those 'massive systems'.

undoubtably though, Sony will devise a large box stuffed with many PS3-based BEs and VSs, probably with more embedded memory, to do similar things that the GSCube did in 2000-2001. now those will certainly reach and exceed 1 tflops.

 

[David_South#1]

Thank you Megadrive,
It was challenging to imagine a Broadband Engine as a single chip.
So I did some looking and chanced upon Regenta (Regatta?, err M-C.M ).

The way Processing Elements are islands of processing stood out to me.
In the patents is says the PE's of a BE will be linked by highspeed bussing.

Coincidentally,
the diagram of an MCM is in fact 4 (processing elements) chips bundled into a bussing 'module'.
Not only this but each (element) chip has multiple cores, again akin to cell.
So for me at least, an MCM is very representary of today's BE.

BTW,
IBM's ideas for MCM design, go further than just one MCM, with O-so-neato visions just like yours.

 

[Megadrive1988]

when Nintendo's Dolphin (Gamecube) was still in development in 1999, several websites were claiming that IBM was claiming some tremendous leaps in performance, even over the then-new Emotion Engine. I think that Power4 had been decribed at that point, and that's what I was thinking Gekko would be, a Power4 MCM (boy was I wrong).

we know a Power4 (and I think Power5 as well) MCM has / can have 8 cores which you get from four 2-core CPUs packaged together, thus the MCM.


being very optimistic (and perhaps even unrealistic) towards Playstation3,
I think it's HIGHLY likely that the CPU and perhaps GPU also, will be MCM(s).

 

[PC-Engine]

Heat and cost will be major factors if MCMs are used in PS3.

 

[V3]

when Nintendo's Dolphin (Gamecube) was still in development in 1999, several websites were claiming that IBM was claiming some tremendous leaps in performance, even over the then-new Emotion Engine. I think that Power4 had been decribed at that point, and that's what I was thinking Gekko would be, a Power4 MCM (boy was I wrong).

They did consider multicore and multiprocessor, but went with superscalar, here a slide from presentation from Embedded Forum sometime ago by Dean Amini, IBM Microelectronics, Director, Advanced Personal Technologies:

Gekko Tradeoffs
Processor Organization
- Options: Single issue, superscalar, multi-core, multiprocessor
- Choice: Superscalar for high performance, lower complexity
On-chip memory
- Options: L1 cache, L2 cache, embedded DRAM, SRAM
- Choice: separate L1 caches, unified 256KB L2, L1 cache locking and DMA for efficient data movement
Floating point support
- Options: Single FP pipeline, dual pipeline, vector engine
- Choice: Dual pipeline for higher performance while maintaining register architecture

 

[Megadrive1988]

cool stuff, V3

 

[archie4oz]

They did consider multicore and multiprocessor

Not very seriously though...