Low-K process explanation

[KimB]

Ideally you don't want any charge to move through the gate. This leakage current is useless to the operation of the transistor. The charges whose motion is more important are those within the bulk silicon below the gate dielectric.

Anyway, since we're on the subject of transistors and whatnot, I'd just like to mention that Intel plans to move to 45nm by 2007. I just have to say that this is very close to the limits of silicon technology. At this size, each transistor will have roughly 100 mobile electrons. That is getting dangerously close to a barrier we will reach all too soon: too few electrons means that the statistical calculations that determine the behavior of transistors will no longer be valid. Transistors will behave completely differently, and thus new technology will be required to shrink devices smaller.

 

[asicnewbie]

RCdelay= 2ρε(4L²/P²+L²/T²)

The speed of an electrical signal in an IC is governed by two components – the switching time of an individual transistor, known as transistor gate delay, and the signal propagation time between transistors, known as RC delay (R is metal wire resistance, C is interlevel dielectric capacitance):

RCdelay= 2ρε(4L²/P²+L²/T²) ,

where: ρ is metal resistivity, ε – permittivity of the interlevel dielectric (ILD) (ε is referred to as k in this field), L – line length, P – metal pitch, T – metal thickness.

In the academic sense, that is fundamentally correct.

However, in modern DSM (deep submicron) design, with tens of millions of transistors packed onto a single die, formerly '2nd and 3rd order' parasitic effects become 1st-order effects (like crosstalk, IR drop, etc.) Back in the 0.65u days, a 0.2v drop from rail (3.3v) was inconsequential. In a modern 0.13u process (1.2v rail), a 0.2v drop severely impacts signal-propagation time (due to slower RC-charging.) Crosstalk (signal integrity) is an especially nasty issue to analyze, because it is dependent on the (dynamic) values of adjacent signal lines.

These phenomena have been known for a long time, but have only recently become critical, since their effects weren't significant at older process nodes. Now they can make or break a tapeout.

> I'd just like to mention that Intel plans to move to 45nm by 2007.

Given Intel's persistent difficulties with 90nm, I guess we'll have to wait and see whether Intel can stick to this timetable.

 

[KimB]

> I'd just like to mention that Intel plans to move to 45nm by 2007.

Given Intel's persistent difficulties with 90nm, I guess we'll have to wait and see whether Intel can stick to this timetable.

Given the ~100 mobile electrons/holes per transistor at these sizes, we're getting into the extreme quantum realm. I expect massive difficulties.

 

[Scarlet]

Interconnect geometry *does* dominate density

"The transistors are below all of the interconnects. The interconnects don't affect the spacing of the transistors (much)."

The truth of this statement varies depending upon what you are building. In the SRAM case cited, the interconnects and the transistors themselves are extremely regular. Thus their behavior and the behavior of the interconnects is very predictable. It is for this reason in the early stages of a new process that SRAMs are used as development vehicles and are frequently the initial products, to be followed closely by PLDs. SRAMs more-or-less establish the upper bound of density. Also the structure of a memory array lends itself to very dense interconnects.

The situation is different when you have individual transistors forming gates, the gates of which are used in logical structures that vary between neighbors, and the logical structure themselves attaching to signals which can go anywhere on the die.

Quite frankly the density of a graphics process is far below that of an SRAM, primarily because the interconnects dominate density more than transistor size.

It's funny in a way - everyone pays attention to transistor geometry size, but the fact is that the interconnect geometries have more to do with how much you can squeeze onto a chip (these days).