Panajev2001a
Veteran
One thing at a time ( Vince is correct in saying that SCE didn't just take Blue Gene's Cellular architecture and pasted on SIMD engines, although we know that IBM did take more than some inspiration form their own R&D labs and what they have been working on in the past 10 years or so... clearly, at least some ideas that arrived in the development of the Cellular Architecture used in the various Blue Gene projects also made its way into what Sony, IBM and Toshiba defined as Cell architecture )...
PlayStation 2 and Saturn...
Let's see... second SH-2 with 2 KB of cache and 2 KB of Work RAM, VU1 has 16 KB of Instruction Memory and 16 KB of Data memory and direct path to the GIF and the VU0 without using the FSB and messign with memory transfers...
The custom DSP, for Matrix operations, was "intelligently" put inside the DMA controller... this DSP had local registers, but not much noticeable local memory to buffer data before having to send it to RAM where the VDPs or one of the SH-2s could pick it up...
Do we need the DSP work on some data from memory ? Ok take some sleep SH-2s because you won't have work to do for a while ( doubling the clock frequency of that DSP == harder than adding a second SH-2... ah, let's add another SH-2... )... oh does the master SH-2 want to update memory so that the other SH-2 can read the data ( basic data sharing between the SH-2s ) ? Perfect, the DSP and the slave SH-2 have to sit on their butt-cheecks now...
Oh yeah... I forgot with that 2 KB of Work RAM and that unified 2 KB L1 cache the slave SH-2 must have "some" mileage...
Wrong... you are assuming that SCE just paid and Toshiba delivered the processor... bull-shit, the VUs implementation did come from Toshiba, but the rest had heavvy collaboration between SCE and Toshiba engineers.
You treat SCE as if they had no real engineers... well you are wrong, but you dissing SCE is nothing new.
IBM had a lead in designing Cell, but Toshiba ( Japan 1st semiconductor manufacturer ) and Sony ( who are climbing up the ladder of Japan semiconductor producers ) did help defining what the architecture was going to be...
See you are inconsistent... first Kutaragi did made Cell the sucky thing Deadmeat thinks it is, then SCE is only a paying customer...
And a Yugo and a BMW are both built around an engine, 4 tires and a wheel...
To call the SCU a pwoerful DMA engine efficiently shifting data around is a bit of an over-statement...
It's like I took a GPU NV2A class ( no local VRAM ), a Pentium III and used an UMA approach with PC133 SDRAM... but...but the Xbox was built around the same scheme it must suck too...
Do you realize that to pass data to the SCU's DSP or to the slave SH-2 you have to stall the VDPs ( in the case that they are waiting for data coming from main RAM ) ?
On a second thought I agree with your statement and I will correct it a bit...
Both are designed on same architectural principle, a distributed processing architecture built around a powerful DMA engine shifting data around: one was designed intelligently ( PlayStation 2 ) and the other was put together at basically the last minute ( Saturn ).
PlayStation 2 and Saturn...
Let's see... second SH-2 with 2 KB of cache and 2 KB of Work RAM, VU1 has 16 KB of Instruction Memory and 16 KB of Data memory and direct path to the GIF and the VU0 without using the FSB and messign with memory transfers...
The custom DSP, for Matrix operations, was "intelligently" put inside the DMA controller... this DSP had local registers, but not much noticeable local memory to buffer data before having to send it to RAM where the VDPs or one of the SH-2s could pick it up...
Do we need the DSP work on some data from memory ? Ok take some sleep SH-2s because you won't have work to do for a while ( doubling the clock frequency of that DSP == harder than adding a second SH-2... ah, let's add another SH-2... )... oh does the master SH-2 want to update memory so that the other SH-2 can read the data ( basic data sharing between the SH-2s ) ? Perfect, the DSP and the slave SH-2 have to sit on their butt-cheecks now...
Oh yeah... I forgot with that 2 KB of Work RAM and that unified 2 KB L1 cache the slave SH-2 must have "some" mileage...
After all, CELL is an IBM baby and SCEI is a paying customer, much like EE was a Toshiba baby and SCEI was the paying customer.
Wrong... you are assuming that SCE just paid and Toshiba delivered the processor... bull-shit, the VUs implementation did come from Toshiba, but the rest had heavvy collaboration between SCE and Toshiba engineers.
You treat SCE as if they had no real engineers... well you are wrong, but you dissing SCE is nothing new.
IBM had a lead in designing Cell, but Toshiba ( Japan 1st semiconductor manufacturer ) and Sony ( who are climbing up the ladder of Japan semiconductor producers ) did help defining what the architecture was going to be...
See you are inconsistent... first Kutaragi did made Cell the sucky thing Deadmeat thinks it is, then SCE is only a paying customer...
Both are designed on same architectural principle, a distributed processing architecture built around a powerful DMA engine shifting data around.
And a Yugo and a BMW are both built around an engine, 4 tires and a wheel...
To call the SCU a pwoerful DMA engine efficiently shifting data around is a bit of an over-statement...
It's like I took a GPU NV2A class ( no local VRAM ), a Pentium III and used an UMA approach with PC133 SDRAM... but...but the Xbox was built around the same scheme it must suck too...
Do you realize that to pass data to the SCU's DSP or to the slave SH-2 you have to stall the VDPs ( in the case that they are waiting for data coming from main RAM ) ?
On a second thought I agree with your statement and I will correct it a bit...
Both are designed on same architectural principle, a distributed processing architecture built around a powerful DMA engine shifting data around: one was designed intelligently ( PlayStation 2 ) and the other was put together at basically the last minute ( Saturn ).