Little bits from Kahle's pat application everyone overlooked

[Deadmeat]

http://appft1.uspto.gov/netacgi/nph...)&OS="Kahle"+AND+"IBM"&RS=("Kahle"+AND+"IBM")

On CPU

102 may be implemented as a general purpose microprocessor such as a PowerPC.RTM. type processor from IBM Corporation.

So it is not exactly a high-end PowerPC like that of Xbox's Power5.

On APU

A vector operation might, for example, add two 64-entry, floating-point vectors to obtain a single 64-entry vector. The vector instruction may be the functional equivalent of an entire DO loop, in which each iteration of the DO loop includes computing one of the 64 elements of the result, updating the loop indices, and branching back to the beginning of the DO loop.

Single instruction 64-way add? There is no way this instruction is hardwired. The APU Vector instructions are virtual.

The depicted embodiment of attached processor 110 further includes logic suitable for performing one or more mathematical functions in the form of a set of vector functional units. The functional units depicted include a floating point add unit 210, a floating point multiply unit 212, a floating point divide unit 214, an integer unit 216, and a logical unit 218.

One FMAC, One FDIV, One Integer, and One branch. The vector instructions must be virtual...

The set of attached processors 110 may account for 50% or more of the total die area whereas each individual attached processor may account for less than approximately 5% of the total die area.

This confirms One CELL chip = One PE(For now).

 

[Paul]

Noone cares about this shit.

Suzuoki's patent is all that matters.

 

[Deadmeat]

..

Suzuoki's patent is all that matters.

Suzuoki is some high ranking executive who takes credit for other's work in Japanese tradition.

James Kahle is the chief CELL architect and a real systems engineer, however....

It does answer a lot of questions, like how SCEI were going to pack 9 APUs per PE(Because each APU is simple and comparable to ARM), and the actual composition of individual CELL chip(1 Chip = 1 PE, not 4 like some people are dreaming here).

 

[Paul]

...

 

[Panajev2001a]

Deadmeat this is only one of the patents relative to the technology: I gave you at least 3:


"Processor with Redundant Logic" ( James Kahle, chief architect of CELL in IBM )

http://makeashorterlink.com/?M1B322DC6


"Simmetric Multi Processor System" ( James Kahle, look at FIG.2 )

http://makeashorterlink.com/?B3D322DC6


"Processor Implementation having unified scalar and SIMD datapath" ( Michael Karl Gschwind, Harm Peter Hofstee, Martin Edward Hopkins... this is basically one of the nicest APU patents together with Kahle's one and what we find about the APUs in Suzuoki's CELL patent ).

http://makeashorterlink.com/?M1F352DC6


"Processing Module for Broadband Networks" ( this is Sony's own Masakazu Suzuoki's CELL patent )

http://makeashorterlink.com/?T1C363DC6

 

[Panajev2001a]

http://makeashorterlink.com/?M1F352DC6

This one is the most relevant as connects the IBM's APU work to the STI work which has, we can say, been summarized by Suzuoki's patent.

 

[Deadmeat]

...

It's that 4Ghz 32APU 1TFLOPS monster in the patent.

According to IBM schedule, you will not see anything approaching teraflop until the end of this decade.... So if you don't mind hanging around until 2010, please do so.

Anyhow, the actual CELL configuration dispute is settled with this single line..

The set of attached processors 110 may account for 50% or more of the total die area whereas each individual attached processor may account for less than approximately 5% of the total die area.

If 9 APUs eat up only 50% of die while the PPC core and DMAC takes up the remainder, you can be sure that each APU has to be very very simple and limited in capability.

 

[Paul]

According to IBM schedule, you will not see anything approaching teraflop until the end of this decade.... So if you don't mind hanging around until 2010, please do so.

Yea, using general purpose cores. BE is comprised of VPU's, the Floating point numbers are inflated. IBM has no use for BE.

Anyhow, the actual CELL configuration dispute is settled with this single line..

Uhmm no?

Toshiba and SCE are building the Broadband Engine and are trying to make the thing a Teraflop, deal with it.

 

[Guden Oden]

Deadmeat, weren't you warned publically not to make threads for no other purpose than pissing on Sony or else you'd get banned?

...So...

Why are you at it again, got a death-wish or something?

 

[Deadmeat]

...

Toshiba and SCE are building the Broadband Engine and are trying to make the thing a Teraflop, deal with it.

Whatever the thing inside PSX3 will be called, it won't have more than 1 PE due to fab process limitations.

Everyone agrees that Intel has the best yielding and best performing fabs in the industry, so take Intel's numbers as benchmark and degrade them to get CELL@65 nm numbers. And Intel certainly isn't planning to build half-a-billion transistor desktop CPUs with their 65 nm process....

 

[Paul]

Whatever the thing inside PSX3 will be called

Broadband Engine.

it won't have more than 1 PE due to fab process limitations.

Time will tell, I'm not going to debate this anymore.

 

[Panajev2001a]

Re: ...

Toshiba and SCE are building the Broadband Engine and are trying to make the thing a Teraflop, deal with it.

Whatever the thing inside PSX3 will be called, it won't have more than 1 PE due to fab process limitations.

Everyone agrees that Intel has the best yielding and best performing fabs in the industry, so take Intel's numbers as benchmark and degrade them to get CELL@65 nm numbers. And Intel certainly isn't planning to build half-a-billion transistor desktop CPUs with their 65 nm process....

Intel is not designing anything of the scale of CELL, nothing that points heavvily on SIMD vector processing.

Whoa, Intel does not use non destructive instruction formats and FP MADD in x86 SSE, so ?

Intel will not build something like CELL because they have other ideas for the Desktop and Server market for x86 and for Itanium as well ( although they plan to go more and more multi-core with IPF ).

Intel has incredibly high margins on their Desktop chips: Sony will start loosing money on Broadband Engine chips in PlayStation 3 and they will have a 45 nm die-shrink right behind the corner from PlayStation 3's launch ( capacitor-less e-DRAM = massive chip area reduction for e-DRAM heavvy chips ).

 

[nobie]

Re: ...

Everyone agrees that Intel has the best yielding and best performing fabs in the industry, so take Intel's numbers as benchmark and degrade them to get CELL@65 nm numbers. And Intel certainly isn't planning to build half-a-billion transistor desktop CPUs with their 65 nm process....

That situation is a little different, regardless of fab capibility. Intel sells processors for profit. Sony will sell PS3 for a loss.
Intel probably COULD make their own BE, but they would have to sell it for >$1000 to maintain their profit margins. It's a business issue, not a technology issue.

 

[Megadrive1988]

hey it looks like I will get a word in before this thread gets locked.


I guess we will just have to wait a few months, or upto 1 year, before we know how many processors are on PS3's CPU die, and how many are on the GPU die.

1 PE = 1 PU/CPU core + 8 APUs + Local Storage + other stuff.

not sure where we got 9 APUs from.

 

[nAo]

not sure where we got 9 APUs from.

one APU is redundant, in the case one APU per PE is not functional you can activate the nineth APU without sacrifying the microchip.

ciao,
Marco

 

[V3]

I am still not crossing out the possibility of MCM Broadband Engine, with 4 PE chips, crossbar memory interface and 64 MB DRAM chip, all in one compact package.

They'll have way better yield this way.

 

[jvd]

Some of you should be ashamed of yourselves for some comments made in this thread .