"leaked" NV30 & NV35 specs.

Discussion in 'Architecture and Products' started by Nappe1, May 14, 2002.

  1. arjan de lumens

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    Umm, no. After primitive assembly, 3 full vertices are attached to each triangle, so you would end up sending 3 times as much data across the interface for no apparent gain. Other than replicating up data, primitive assembly is a fairly trivial task and can be done essentially instantly as vertices become ready. So it would make more sense to put vertices rather than full triangles into the FIFO. ALso, the only gain from using such a FIFO would be in situations where the scenery would otherwise toggle back and forth between being fillrate bound and T&L bound.
     
  2. Yannis

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    Hi,

    I think these specs are fake :)

    They don't match with Nvidia engineering philosophy. Nvidia has always been fan of elegant and cost effective solutions. Separating the whole chip to two sub-processors (chips) just doen't resemble Nvidia.
    It looks much more like 3dfx...
    If Tarolli managed to change a whole company's philosophy, that had driven it to sucess the last 3 years and also bought his own company 2 years ago then what can I say...

    Yannis
     
  3. ERP

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    In my experience this is pretty much anywhere you have large amounts of geometry. Bear in mind that on average somewhere between 30 and 50% of the drawn tri's in a scene have no pixels (backface culled or scissored) and are therefore transform limited. And even with very small tris 10 pixels or so, Geforce 4 will end up fill limited.

    I had considered placing the division prior to primitive assembly, but then the rasteriser requires access to index buffers. The extra data required for transmission would probably offset the additional complexity though.
     
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