arjan de lumens
Veteran
ERP said:Although I actually doubt that NVidia will use a two chip solution.
If you were to split the existing GF4 pipeline directly after primitive assembly placing a largish fifo (I assume the two chips would allow this)between the two chips you'd probably see a significant performance increase in high stress real world situations.
Umm, no. After primitive assembly, 3 full vertices are attached to each triangle, so you would end up sending 3 times as much data across the interface for no apparent gain. Other than replicating up data, primitive assembly is a fairly trivial task and can be done essentially instantly as vertices become ready. So it would make more sense to put vertices rather than full triangles into the FIFO. ALso, the only gain from using such a FIFO would be in situations where the scenery would otherwise toggle back and forth between being fillrate bound and T&L bound.