That could be Montreal, which slides point to having a full 1MiB of L2 per core.
If Shanghai's L3 were to become approxmately as dense as Intel's, there would be room for 1.5 MiB of extra L2 chip-wide right there. Further tweaks on the L2 density and perhaps other changes might have enough additive improvement to enable the cache increase with a hopefully small die size increase.
edit:
There's also the option of just bloating the core back to Barcelona's die size. Going by the 7.5 mm2 per MiB, going from 266 to 285 is 19/7.5, which would at least allow the room for the cache arrays.
The rumors that Montreal could be an MCM seem hard to justify with doing this. Actually they seem hard to justify even now, given Shanghai's current size.
If Shanghai's L3 were to become approxmately as dense as Intel's, there would be room for 1.5 MiB of extra L2 chip-wide right there. Further tweaks on the L2 density and perhaps other changes might have enough additive improvement to enable the cache increase with a hopefully small die size increase.
edit:
There's also the option of just bloating the core back to Barcelona's die size. Going by the 7.5 mm2 per MiB, going from 266 to 285 is 19/7.5, which would at least allow the room for the cache arrays.
The rumors that Montreal could be an MCM seem hard to justify with doing this. Actually they seem hard to justify even now, given Shanghai's current size.
Last edited by a moderator: