What could be interesting, if some rumors prove true, is that Nehalem's L2 will only be 256 KiB.
Nehalem will likely have a cache advantage still, but the relative difference wouldn't be anywhere near as bad as the current cache disparity.
The downside is that Nehalem would have replaced that advantage with a potentially superior memory controller, and I have a sneaking suspicion that Intel's L3 isn't going to have the pathetic latency numbers Barcelona's last level has.
Let's hope Shanghai's latencies improve.
I wouldn't be surprised if Nehalem's L2s are around 256KB-512KB. They are probably optimized for bandwidth/latency, given the beefy cores they have to feed. The large L3 will provide coverage.