Leaked Intel Nehalem performance projections over AMD Shanghai

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It appears that the rumors about Intel’s next major microprocessor “Nehalem” being a huge juggernaut may be true according to leaked documents from Sun Microsystems (removed Sunday night). The slides appear to be inadvertently placed on Sun’s publicly accessible website and “jokerman” posted the link on Aceshardware (thanks to tip from ZDNet reader JumpingJack). The slides looks like the real thing meant for Intel’s partners and they’re probably well known in the server industry.
http://blogs.zdnet.com/Ou/?p=1025

Nehalem seems to be a real beast.

Here is a link to the now pulled slides: http://rapidshare.com/files/94740674/Sun_Intel_Road_20Show_Austria.pdf

If you have any objections to the slides being linked to here, please notify me or a moderator so the post can be edited and the link removed.
 
The figures are Specrate numbers, so Nehalem EP's numbers looks as good as they are in part because of SMT. Assuming the Nehalem EP on the slides is Gainstown, it's 2 threads on each of 4 cores.

There's no strong impetus, it seems, to post the non-rate values on the server-oriented slides. Nehalem's gain over its predecessors might be more modest there.

AMD's Montreal core seems poised to fall in the middle of the year between Gainstown and Beckton (assuming it arrives at the early part of its time frame, something no AMD chip has managed to do for some time).

As nice as SMT is, there might be a switch in the rate numbers for a quarter, perhaps two.
This would assume that AMD can get more competitive clocks and other improvements that are so lacking right now.
Beckton, however, would swing the pendulum back.
 
http://blogs.zdnet.com/Ou/?p=1025

Nehalem seems to be a real beast.

Here is a link to the now pulled slides: http://rapidshare.com/files/94740674/Sun_Intel_Road_20Show_Austria.pdf

If you have any objections to the slides being linked to here, please notify me or a moderator so the post can be edited and the link removed.

The question is how many cores is that comparison derived from? If its 4 then its very impressive but if its 8, which should be the top Nehalem configuration then its not all that incredible (although still good).
 
If the EP suffix still means the same on those slides as elsewhere, then the chip should be Gainstown, which is the 4-core.

Beckton is the 8-core, and it isn't due until the end of 2009, if the rumor mill is correct.
 
If the EP suffix still means the same on those slides as elsewhere, then the chip should be Gainstown, which is the 4-core.

Beckton is the 8-core, and it isn't due until the end of 2009, if the rumor mill is correct.

*end* of 2009? Last I heard was beginning of 2009. Has there been a slip I haven't heard about?
 
*end* of 2009? Last I heard was beginning of 2009. Has there been a slip I haven't heard about?

The wiki on the 8-core Nehalem says Q4 2009, other places I've seen for release dates have said something like 2H 2009.

Beckton is the big-tin Xeon MP variant, which at least from history tends to lag a fair amount behind the other variants.
 
If the EP suffix still means the same on those slides as elsewhere, then the chip should be Gainstown, which is the 4-core.

Beckton is the 8-core, and it isn't due until the end of 2009, if the rumor mill is correct.

Thats pretty damn impressive for only 4 cores then :smile:

I just hope it translates into realo world performance. Hell, even half that increase would be impressive!
 
It's 4 cores, though the numbers didn't indicate if the tests were done with 8 threads.
The benchmarks were SPECrates, which can show decent gains from multithreading.

For many desktop workloads, the non-rate numbers would be a stronger indicator of general performance, and Intel didn't disclose those numbers.

Hyperthreading may lead to modest gains over the previous generations on the desktop, and the implementation will likely prove more successful than the unimpressive Netburst variant.

The IMC and other tweaks should help, but I haven't seen much speculation that Nehalem's single-threaded performance will improve as greatly.
 
Sounds like you're right. At least, if L'inq is to be trusted.

"until the 8-core Beckton Nehalems replace it a year or so later"

"it" being Dunnington of course, which is slated to arrive just before 4-core Nehalem.

Crap, when the hell did that happen? As recent as the latest IDF I'd been hearing "8-core Nehalem: end of '08/beginning of '09".
 
Shanghai can be clocked above 3GHz, according to several sources.

I wouldn't count on any rumours about AMD. There have been so many saying how good things will get real soon but pretty much none of them has been true.

I personally lean more towards Shanghai debuting at <2.6GHz with <100W TDP late this year because "this is what customers demand", at least that was said about those <2GHz barcelonas :)
 
I bet shanghai stock clock Shanghai above 4.1 GHz! :eek: I´m serious. Wanna bet?

Hey, only 4.1GHz? Pulling Scientia I would have said combining retail 65nm SoI CPUs running at 4.7GHz with the super-duper immersion litho on 45nm and all the other buzzwords it should run at least twice that frequency!

:p
 
Does anyone here realistically think that AMD will be able to ship Shanghai during 2008? And especially at 2.8 GHz and above? Based on their track record for that last few years I'm not optimistic, although I would welcome it.

And what is known about the improvements in Shanghai compared to the current Phenoms?
 
The IMC and SMT in Nehalem should result in higher TDPs. (edit: higher than they would be otherwise. Intel's process at 45nm is very good at lowering power consumption in general. AMD's is not a known quantity, and published details indicate Intel's process is better)

The IMC in Opteron consumes some amount of power, but I haven't seen a breakdown for the latest models. The number for the DDR2 controller on K8 was something less than 10 Watts.

The Gainstown chip's triple-channel controller should consume more than a dual channel at the same process.
DDR3 might lower the consumption, but it's something that might be in the 10W neighborhood.

SMT can be highly variable. Increased utilization can really raise peak power draw if the thread instruction mix is right.

SMT's die size impact is difficult to quantify.
IBM said POWER5's SMT bulked the die up by 25%, while Intel said Hyperthreading increased the P4 die by 5%.
Perhaps Nehalem will split the difference?

What could be interesting, if some rumors prove true, is that Nehalem's L2 will only be 256 KiB.
Nehalem will likely have a cache advantage still, but the relative difference wouldn't be anywhere near as bad as the current cache disparity.
The downside is that Nehalem would have replaced that advantage with a potentially superior memory controller, and I have a sneaking suspicion that Intel's L3 isn't going to have the pathetic latency numbers Barcelona's last level has.
Let's hope Shanghai's latencies improve.
 
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