Larrabee using the Atom core?

[Per B]

I don't know if it's been discussed, by isn't it likely that Larrabee is using the x86 core found in the new Atom CPU? All connected à la Terrascale?

I guess they still would need some dedicated graphics hardware though, unless they put all their eggs in the ray-tracing basket.

Thoughts on this?

 

[AnarchX]

Sure it is In-Order too, but there some differences: 4 threads each core, SIMD16 vector calculating.

Some stuff to read:
http://download.intel.com/technology/itj/2007/v11i3/vol11-iss03.pdf

 

[Arun]

It'd certainly be a pretty good match (Silverthorne is 2 threads/core, and I wouldn't be surprised if that was easy to extend, at least compared to developing a new core) as you'd 'just' need to add a SIMD16 vector unit and you're done. What is also very interesting is that the die sizes match: Silverthorne's die size is ~25mm², but the actual core size was estimated to be only ~9mm² based on die shots. At the same time, that fits nicely with this picture: http://beyond3d.com/images/articles/IntelFuture/Image9-big.jpg

The problems, however, are numerous:
- Silverthorne was synthetized with power-optimized cells, which provide worse perf/mm². So the RTL might be reusable, but none of the synthesis would probably be (not a big problem though).
- In previous discussions on the forum, it was concluded that the timeframes likely didn't match for that kind of reusage to take place.
- The Larrabee team is rumoured to be extremely independent from the rest of Intel.
- That 10mm² includes the SIMD16 unit; the ~9mm² doesn't, it simply supports SSE.

Certainly I'd be a pretty big fan of reusing the Silverthorne architecture for Larrabee (if done properly) because it'd also provide decent single-threaded performance (would also help to attack the Sun Niagara/Rock market), although it might hurt overall perf/mm² a little bit.

 

[3dilettante]

I thought earlier that the hypothetical 10mm^2 core size included L2, but I looked again at the slide and I guess not.

Silverthorne might be a guide to some of the philosophy behind Larrabee.
I'm curious about the reason why Silverthorne implmented its L1 data cache as a register file.
It would seem that it would hurt density, but perhaps it makes up for alignment issues on SIMD ops?
That might be a useful addition to Larrabee.

Larrabee should dispense with the bulk of the Bus Interface Unit, since each individual core won't be addressing the outside world.
If Intel were to merge the FP cluster with the integer cluster and cut the ring bus interface to under 1/2 the size of the FSB interface, it would have floor space for an FP cluster triple the current size.

If arranged as MEC-[FEC+IEC]-FEC with the ring bus stop sort of planted to a side, it might be possible to cram everything in with enough engineering work going for maximum density.
I'm not saying Intel would do it, but maybe it could be done with only a little expansion in core size (not to mention other possible costs in performance or functionality).

 

[Mike11]

It'd certainly be a pretty good match (Silverthorne is 2 threads/core, and I wouldn't be surprised if that was easy to extend, at least compared to developing a new core) as you'd 'just' need to add a SIMD16 vector unit and you're done. What is also very interesting is that the die sizes match: Silverthorne's die size is ~25mm², but the actual core size was estimated to be only ~9mm² based on die shots.

Since Larrabee is bound for late 2009 or 1H/2010 it could very well be a 32 nm chip. So die size comparison is highly speculative (45 nm vs. 32 nm).

 

[kyetech]

Since Larrabee is bound for late 2009 or 1H/2010 it could very well be a 32 nm chip. So die size comparison is highly speculative (45 nm vs. 32 nm).

No offence Mike11 but I think Arun might already know that.