I think the latest Itanium version has separate integer and fp multipliers now.
The biggest issue I have with the itanium is more of a philosophical one, in that its heavy dependence on compiler optimization and profiling can make the chip too inflexible for an instruction stream that isn't spoonfed to it.
I do like the attempt to get some regularity in the ISA, rather than have a half dozen predecode and decode stages in the chip like x86 requires in order to figure out if a byte stream is any of several possible instructions.
It may turn out that future chips will be more like a more lithe Itanium than a buff Opteron, or a lot of tiny Itaniums. There are serious roadblocks on the way, and while ISA isn't the primary problem, it can be a serious bottleneck.
The biggest issue I have with the itanium is more of a philosophical one, in that its heavy dependence on compiler optimization and profiling can make the chip too inflexible for an instruction stream that isn't spoonfed to it.
I do like the attempt to get some regularity in the ISA, rather than have a half dozen predecode and decode stages in the chip like x86 requires in order to figure out if a byte stream is any of several possible instructions.
It may turn out that future chips will be more like a more lithe Itanium than a buff Opteron, or a lot of tiny Itaniums. There are serious roadblocks on the way, and while ISA isn't the primary problem, it can be a serious bottleneck.