version said:
Err, yeah that was the point, IF the dot product is not a 1 cycle operation, then it's a total waste.
ISSCC 2005
- Thread starter ChryZ
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Err, yeah that was the point, IF the dot product is not a 1 cycle operation, then it's a total waste.
MfA said:
Does that just not give u 4 dot products at the same time, after however many cycles they need to process them? Which is mostly the same, but if u just need 2 or 1, it's still a waste. I might be picking nits but that would only be efficient when multiples of 4 dot products are needed, right?
Panajev2001a
Veteran
DeanoC said:
Well, for those calculations use the VMX unit in the PPE, it might be better suited
.Panajev2001a
Veteran
nAo said:
Increase data signalling rate to 6.4 GHz and/or use smaller modules like 256 Mbits each
.hmm. i actually like the multiply-add setup found in cell. and instead of putting in any single high-cost dot-prod op in the other pipeline as guys have expressed, i'd rather have that pipeline having more of the same.. not that it would be viable.
statistically speaking, it makes sense to improve the en-mass dot prod as much as possible, leaving the sporadic dot prods to the add-hoc skills of the coder. hell, if circumnstances allow you can come up with a soup of scalar mul and add ops for a sporadic dot prod and still get away with that. its all a matter of statistics at end of the day ; )
statistically speaking, it makes sense to improve the en-mass dot prod as much as possible, leaving the sporadic dot prods to the add-hoc skills of the coder. hell, if circumnstances allow you can come up with a soup of scalar mul and add ops for a sporadic dot prod and still get away with that. its all a matter of statistics at end of the day ; )
Megadrive1988
Veteran
interesting usenet post i just found
http://groups-beta.google.com/group/comp.parallel/msg/0984291487397f46?dmode=source
Newsgroups: comp.parallel
and so far, the only reply:
and did that guy in the original post say he wants to built a 4 TeraFlops Double Precision processor? i don;t think that'll be possible anytime soon since the first generation Cell is only 25~30 DP GFlops.
http://groups-beta.google.com/group/comp.parallel/msg/0984291487397f46?dmode=source
Newsgroups: comp.parallel
and so far, the only reply:
and did that guy in the original post say he wants to built a 4 TeraFlops Double Precision processor?
i don;t think that'll be possible anytime soon since the first generation Cell is only 25~30 DP GFlops.I think the demand for dot product calculations will slightly outstrip the PPE's capability.Panajev2001a said:Well, for those calculations use the VMX unit in the PPE, it might be better suited
You guys are forgeting something. The amont of ram availiable would also be able scale up with the amount of PPE's. Thus with a 2 PPE setup you would have a max of 512MB's of ram and so on as you add more. I'm not sure if it would be an individual ram pool for each PPE or it could be shared across the flexIO though.
And the horizontal summing can't be done with floats either... As for "improving" unless you're speaking of other SIMD architectures, AltiVec hasn't changed a bit ISA wise. The only differences have been with the various quirks with regards to physical implimentations...
ClearSpeed CSX600:
• 250 MHz clock
• 96 high-performance processing elements
• 576 Kbytes PE memory
• 128 Kbytes on-chip scratchpad memory
• 25,000 MIPS
• 50 GFLOPS single or double precision
• < 5 W typical power dissipation
• 25 GMAC/s integer multiply-accumulate
• 250K 1,024-point complex floating-point FFTs per second
Each PE contains:
• Integer ALU
• 16-bit integer MAC
• Superscalar 64-bit FPU
• 128-byte register file
• 6 Kbytes of SRAM
• High speed I/O channel
• 250 MHz clock
• 96 high-performance processing elements
• 576 Kbytes PE memory
• 128 Kbytes on-chip scratchpad memory
• 25,000 MIPS
• 50 GFLOPS single or double precision
• < 5 W typical power dissipation
• 25 GMAC/s integer multiply-accumulate
• 250K 1,024-point complex floating-point FFTs per second
Each PE contains:
• Integer ALU
• 16-bit integer MAC
• Superscalar 64-bit FPU
• 128-byte register file
• 6 Kbytes of SRAM
• High speed I/O channel
Not a technical article, but Jon Peddie attempts to ground things a little:
http://www.jonpeddie.com/index.shtml
http://www.jonpeddie.com/index.shtml
Panajev2001a
Veteran
DeanoC said:
Uhm... might it be a 128x128 bits registers VMX like the one the Xenon PU's use
?Seeing how the PPE was not really covered in much detail at ISSCC, I think there is even further suspicion that basically the PPE and the each of Xenon CPU cores are the same core as some birds were chirping outside my window a long time ago. There are reasons IMHO that the PPE was not talked about in too great detail.
Would this mean that the PPE's VMX unit is the same 128x128 bits registers' monster that are the VMX units in Xenon (they must still not be too huge as they can fit three of them plus three cores as well as 1 MB of L2 in a single chip and likely take less space than CELL's PE).
That's nothing but the classical "People are jumping the gun, and they should not, so somebody has to clarify the situation, even if it means writing a paper bordering condescension, and this somebody is me" kind of article.DaveBaumann said:
People who expect Cell to play a role in the desktop arena are not, necessarelly, unable to understand the Cell strengths and lacunae, and/or the market realities. They're just seeing Cell has a "solid-enough" competitor for the old, old X86. They're just enthusiasts about new technology. Of course, in this case it's pure dreamland fantasy, but enthusiasm and optimism are almost synonym.
I for myself don't believe Cell will do anything to Intel/AMD plans, and if miraculously it does take a microscopic part of the market, that won't change that I don't care about desktop CPU.
It's just that I never understood point of articles like that... It's like saying "Hey, stupid kids, your inabilities to understand and comprehend simple informations, made you, once again, miss the point of all this talk, so since I'm a very a knowledgeable person, I accept to explain you the situation in a very patronizing and conservative way, and then I'll enjoy your lamentations when you'll realize that your foolish hopes and dreams have been crushed by the hard, cold reality."
PS: You may think that I'm overreacting to a simple article written in layman's term... And you'll be completely right, it's Saturday and I'm bored to death by a, bugged like sh*t, huge ass database that don't want to back up correctly. So this explain this useless joke post!
Panajev2001a
Veteran
Uhm... looking at the picture of the PPE available (I only know of this one:
) it would look like two things can be possible:
1.) the VMX unit does not use a 128x128 bits Register File (like the rumored super VMX unit that the Xenon's CPU cores use).
2.) the Register File is subdivided differently from the one in the SPU's and the different layout makes recognition (you cannot see the samer GPR block as in the SPU's) a bit more difficult (this is the option I am leaning towards).
Before this ISSCC presentation we all expected the Xenon cores to have a VMX unit and even though we heard repeatedly that the PU in CELL was at least closely related to the Xenon CPU cores or even being the same thing. Still, a lot of people were surprised to see a VMX unit in the PPE, but the PPE has one.
) it would look like two things can be possible:
1.) the VMX unit does not use a 128x128 bits Register File (like the rumored super VMX unit that the Xenon's CPU cores use).
2.) the Register File is subdivided differently from the one in the SPU's and the different layout makes recognition (you cannot see the samer GPR block as in the SPU's) a bit more difficult (this is the option I am leaning towards).
Before this ISSCC presentation we all expected the Xenon cores to have a VMX unit and even though we heard repeatedly that the PU in CELL was at least closely related to the Xenon CPU cores or even being the same thing. Still, a lot of people were surprised to see a VMX unit in the PPE, but the PPE has one
.If it stepped into a 3D role specifically, possibly, but considering that hasn't been established (and likely won't for a while)--and B3D typically doesn't do console and other specialized 3D parts, instead focusing on PC solutions, I don't suppose we'll be seeing much.pc999 said:BTW will "B3D", make their own article about CELL
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