It could be the other way around. HBM's data rates are not going to be sustainable if the most important traces are not kept short, which means close proximity to the neighboring chip. The rest of the HBM base doesn't need the interposer, or is substantially hindered by it. Fury partially worked around area constraints by having parts of the HBM base extending outside the patterned area of the interposer.
I was being sarcastic...
EMIB's chief insight is that in an up to ~1000mm2 passive interposer of the sort AMD uses, literally only the area of the bridge was what was actually needed for the microbumps and traces.
The test, power, and ground pads use the same comparatively massive solder balls, and the vias drilled through the interposer to service them is part of the additional expense of the interposer.
The costly part of an interposer is the ultra-fine-pitch bumping and performing assembly that doesn't break the ultra-fine pitch joints. The extra area of an interposer for the low-density TSVs is pretty much free. Don't forget this is area from super-low-tech wafers, 65nm, 130nm (I can't remember)?
https://www.3dincites.com/2016/04/2-5d-and-3d-opportunities-for-cost-reduction/
OK so we don't have a TSV cost per mm² there, but the 2.5D pie chart looks favourably upon the costs of TSVs.
Also can you test the EMIB with just the memory in place? With an interposer you can test with just the memory installed, before installing the GPU, defraying some of the assembly yield loss (GPUs lost to bad HBM assembly).
So EMIB costs are not looking favourable head-to-head versus interposer. And, well, we'll never know for sure, because the kind of detailed cost analysis we're looking for never exists...
This and the apparent use of a standard PCIe interface makes me think AMD's chip effort was a modest customization in this regard, since the bumps do not change and Intel would likely worry about most of the mechanical/alignment/assembly concerns.
Oh there's no doubt AMD's effort was low and as you noted earlier in this thread, it frees AMD from having to pay for interposer assembly and HBM inventory.
Unless, erm, AMD actually supplies the complete EMIB sub-assembly, with HBM. Hmm, now I think about it, I wouldn't be surprised if AMD is doing that. It would make sense for Intel to let someone else pay for packaging yield. Especially as there is no EMIB twixt GPU and CPU.