I think there's a number of factors that might go into this.I wonder whether this project started before Ryzen CPU cores were final. Nowadays you have to ask whether it would be simply easier for AMD to integrate Ryzen cores with Vega GPU... Which they did with Raven Ridge. They also now have HBM2 GPU products in Vega 56/64. Why didn't AMD simply do a Raven Ridge APU with scaled up GPU + HBM2?
AMD's architectures, HBM2, market position, and 2.5D integration tech at present leave it limited room to make a client APU of this scale practical.
AMD's situation has it trying to stretch a limited set of silicon designs over as broad a range of segments/volumes as it can. Raven Ridge is already the size of a Ryzen die, which is as far as AMD is willing to go for a die that ranges from the R3 to EPYC price bands.
Raven Ridge would continue existing for volume, cost, and likely power reasons. That would leave AMD having to create a big APU with non-shared engineering, masks, package/socket, interposer, and HBM2.
The cost and complexity adders would not be acceptable at Raven Ridge's physical footprint, but since Raven Ridge exists AMD would have to use its big chip and HBM2 for a limited volume, more complicated platform and product mix management, and probably inferior return on investment for a big and niche chip.
Intel thinks it can make a somewhat equivalent package product, but this looks like it won't be at a volume AMD needs or price it can command--and that's with integration technology that seems more practical for this space, barely.
A custom deal likely means more of the up front cost AMD could not afford was paid, in exchange for less money per chip in the long run. A non-standard socket, the risk of a product flop, AMD's history of flubbing product mixes, package integration, HBM2 procurement (maybe?), and other risk factors become mostly Intel's problem.
Long run, a somewhat less integrated solution should have been possible with Raven Ridge and a Vega discrete, so long as xGMI or a variant for the Infinity control fabric were available to help share power management. While not quite on the level of this solution, it could have overlap without too much specific investment in the niche.
It's not clear that AMD made any provision, which may mean those methods are not ready yet.
Long-run, AMD may need to figure out how it plans to get 2.5D or 3D integration to be more practical. I'm not sure Intel needed to give much insight into EMIB, and AMD's isn't vertically integrated so that it can implement such a packaging method on its own.
If it's customized for Apple, it's also possible there are other tweaks specific to that product that Apple wouldn't want discussed, maybe.The only thing that would make sense is that Apple ordered this chip for the next Macbooks. They already use Intel CPUs and AMD GPUs. Integration saves cost, space and power. Intel still has slightly bit better single thread performance and process advantage, so it makes sense that this is built on top of their tech. This would also explain the secrecy around the project and no news about the launch products. Apple doesn't like talking about their products before the launch.