Intel Skylake-X and Skylake-SP Utilize Mesh Architecture for Inter-Chip Communication
https://www.pcper.com/news/Processo...ze-Mesh-Architecture-Inter-Chip-Communication
Negligible latency differences in accessing different cache banks allows software to treat the distributed cache banks as one large unified last level cache. As a result, application developers do not have to worry about variable latency in accessing different cache banks, nor do they need to optimize or recompile code to get a significant performance boosts out of their applications.
https://www.pcper.com/news/Processo...ze-Mesh-Architecture-Inter-Chip-Communication