http://www.tgdaily.com/2006/07/10/intel_32_core_processor/
While I'm sure this massive parallelism will be for server systems for a few years before it makes its way to home PC's, I still have to say that I didn't expect it quite so soon. The configuration looks pretty beefy, and the architecture will support 4 threads per core:
Back on topic, though, I expect that game software is going to have a lot of catching up to do in the next few years. PPU's? Who needs 'em!
Edit: By the way, there's a more in depth article that is linked from within the above link.
While I'm sure this massive parallelism will be for server systems for a few years before it makes its way to home PC's, I still have to say that I didn't expect it quite so soon. The configuration looks pretty beefy, and the architecture will support 4 threads per core:
I do, however, have to take issue with this following snippet:The first Keifer chip will be manufactured in 32 nm and use eight processing nodes with four cores each. Every node will have direct access to one 3 MB on-die last level cache (LLC) and 512 kB L2 cache. There will be a total of 8 x 3 MB LLC slices that are connected by a ring architecture and represent a total 24 MB of cache.
Well, duh! That shouldn't be remotely surprising.And surprisingly, Intel does not consider AMD's Opteron and successors as Kevet's and Keifer's benchmark. The documents seen by TG Daily aim Keifer at Sun's "Niagara" architecture, which is currently available in the "Ultra Sparc T1" processor. The T1 was launched last year with great fanfare as 1.2 GHz 8-core processor with 3 MB L2 cache and capable of handling a total 32 threads at a peak power of just 72 watts.
Back on topic, though, I expect that game software is going to have a lot of catching up to do in the next few years. PPU's? Who needs 'em!
Edit: By the way, there's a more in depth article that is linked from within the above link.