How do you calculate Bandwight on DDRII?

[elimc]

As I think I've said a couple of times. When comparing for instance DDR400 vs DDRII400 (2 vs 4 way multiplex), the higher multiplexing is used to run the memory array at half the frequency, still at same data rate per pin.

Just to be a little more clear. When talking about the memory array in a DRAM, you mean the part of the chip that actually stores the data, as opposed to the external interface out from the chip. The design of the memory array is not much related to the interface, and the same array could be used for SDR100, DDR200, DDRII400 and RDRAM800.
(RDRAM800 break up the array in more banks though.)

Yea, I think there was a miscommunication between me and you. I think you're stating what I was trying to get at.

 

[NTD]

I'm not sure what you meant there, but I can say that such comparison isn't interesting if you don't say what speed the different memories are:

• Same memory array clock speed.
• Same external bus clock speed.
• Same datarate. (Which is the usual way to denote the speed now.)
• Same cost at certain point in time.
• Fastest available at certain point in time.

Well, like I said, bandwidth and of course at identical clockspeeds. DDR running at 133MHz gives you, theoretically, twice the datarate SDR does at the same clockspeed.

 

[Entropy]

DDR-400 and DDRII-400 DRAM output data at the same rate.

(I thought it deserved to be said on its' own.)
The changes in the DDRII spec help ensure signal integrity and greater ease of scaling the clock upwards.

You guys got mighty technical for a while there, to the point where even the somewhat initiated could get confused.

Entropy

 

[pascal]

IIRC DDR II is:
- 400Mbits/pin for mult-drop configurations, or 3.2GB/s for 64bits bus
- 800Mbits/pin for point-to-point configurations, or 6.4GB/s for 64bits bus

The DRAM core runs at 1/4 the data bus frequency because it uses a prefetch of 4 (burst 4 only, righest common denominator and lower test cost). Also no 1/2 latency and no interruption commands (lower test costs too).

Maybe this PC6400 will use a prefetch of 8???

 

[pascal]

Some kentron pdf file show an alternative using phase shifting for memory
http://www.via.com.tw/en/presentations/JAPAN/KentronQuadDDR.PDF

edited: it looks like they are still discussing about the 8 banks. Also the 4, 8 and 16 burst are available?? See page eleven of this presentation:
http://www.via.com.tw/en/ddr/DDR333 Summit 2002/11