Hofstee on UIUC webcast

[phed]

I did a search for hofstee but couldn't find anything.

Get the video from here: http://www.acm.uiuc.edu/conference/webcast.php

Cell Processor: Motivation, Architecture, Design, Programming and Applications

This talk will present the Cell processor, jointly developed by the STI partnership (Sony-Toshiba-IBM). Cell is a non-homogeneous chip multiprocessor intended for general-purpose applications but with a particular emphasis on multimedia performance.

The Cell processor combines a 64bit Power Architecture(TM) core with 8 Synergistic Processors. In many cases delivers more than an order of magnitude more performance than conventional PC processors. Cell achieves this performance and power efficiency improvement by a new division of labor between the Power core and the Synergistic Processors. Cell allows for a wide variety of programming models, a selection of which will be presented in this talk. We will end the talk by discussing some applications that seem to fit the Cell processor particularly well, and by indicating areas of further exploration.

edit: Ok, the video doesn't have much new, except (at least for me) some clarifications on the role of SPEs and their instructionset and the usage of the local memory.

 

[rendezvous]

As you say, not much that's really new, but it's still a nice find.

It pretty much clarified how multithreading on the PPE core works if you look at the slide he skipped over.
Anothor thing that I thought was interesting was how the SPEs were able to handle scatter and gather operations by building a DMA list that then is executed on the synergestic memory flow controller.

I looked att two other talks too.
The first one was "feature based rendering" and while interesting I don't think it will have its place in consoles this uppcoming generation.
The other was "raytracing on desktops". This talk was a bit of a dissapointment. It was about how they in UIUC will cooperate with Saarland university in designing a raytracing ASIC.

 

[Shifty Geezer]

Anothor thing that I thought was interesting was how the SPEs were able to handle scatter and gather operations by building a DMA list that then is executed on the synergestic memory flow controller.

Interesting point. Rather then going out to fetch data as needed, accumulate DMA's into a batch job, Though there will be the trouble in stalling processing on fetches and the DMA goes out. I think two SPe's in combination would be a good solution. SPE1 processes so far until the random accesses are needed and builds the DMA batch. That data is fetched and sent to SPE2 to perform the necessaries on the recieved data. That'll keep processing running smoothly, but only supports a single fetch. If you need to make multiple random reads and writes juggling processing might get rather tricky.