Haswell vs Kaveri

mczak said:
At least unless there's a specific reason why GT2 could not benefit from more open pages (which is possible maybe GT3 having twice the ROPs could play a role here).
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Interesting idea - the screen is statically split into tiles across the two slices so you'll definitely get somewhat more scattered access in GT3 from that point of view (both ROP and memory reads from the shader). That said, the tiles are pretty small so I doubt it's going to thrash 4K pages or anything like that... how big are the "ranks" we're talking about in the DRAM?
 
A rank is the set of chips that are activated simultaneously by a chip select signal.
The example 2-rank 4GB DIMM from the slide would have 2GB per rank.
 
The exact mapping and policies for memory controllers are part of what I would use the words "special" and "sauce" for if I hadn't become sick of hearing that phrase over the last year.
If there as least some locality to accesses, it would generally be better if addresses were not striped finely across multiple ranks, as hopping back and forth means the access pattern is now forcing a transition where it must unselect one set of chips and select the other with all the physical penalties, synchronization, and wait states needed.

http://globalsp.ts.fujitsu.com/dmsp/Publications/public/wp-sandy-bridge-ep-memory-performance-ww-en.pdf

According to this, at least for these workloads it is better for ranks to interleave with a granularity closer to an OS page.

Channel interleaving can be done more finely, at granularities consistent with cache lines, since having multiple channels means chips aren't fighting over the same wires.

I did see a presentation that gave a 256 byte granularity for GPU memory striping, but that might have been for an old architecture.
 
If demand for them is high they should just start using the 7700's as 7600's.
Alternatively they could released a locked 7700 at ~$130.
 
Production is expensive or low yield?
They have a back catalog of Trinity and Richland to sell as well. Releasing the 7600 makes them less desireable.

It's damn annoying. At this point I'm wondering if they'll exit the highish performance business after Carrizo.
VIA Nano X2 + DX10.1 chipset was like that : good, but you can't buy it. There was even that unobtainable Nano X4 that looked like a small Q6600, the swan song of the adventure then poof.. VIA/Centaur x86 CPU have ended.
 
http://blogs.intel.com/technology/2...adobe-creative-cloud-intel-iris-pro-graphics/

Nice turnaround for Intel compared to 4 years ago.

http://www.anandtech.com/show/3972/nvidia-gtc-2010-wrapup/5

In fact Kevin was rather frank about how Intel’s GPUs and drivers had caused them a great deal of grief, and that as a result they’ve had to blacklist a great deal of Intel product/driver combinations as the drivers advertise features that aren’t working correctly or aren’t stable.
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mczak said:
Yes but the math doesn't work out the slightest bit if you assume GT3 is heavily bottlenecked but GT2 is not, if they both have roughly the same performance in the end (it would essentially mean the GT2 would be not bottlenecked at all by bandwidth, whereas any additional shader capacity the GT3 has is completely wasted due to bandwidth constraints). Because both have very similar performance in the end, both should be equally bottlenecked by bandwidth, therefore both should benefit similarly from dual rank memory. At least unless there's a specific reason why GT2 could not benefit from more open pages (which is possible maybe GT3 having twice the ROPs could play a role here).
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There is a ~70% gap between GT3 and GT3e. GPU frequency difference roughly 15%. Bigger cache and faster CPU helps Iris Pro a bit of course but the gap is way too big. We know from Intel that the cache improves performance almost by 40% in average. This speedup is missing on the GT3 non edram version. With Skylake I hope 25-28W Iris will get some kind of edram too, otherwise it won't look appealing for the price.
 
http://www.phoronix.com/scan.php?page=news_item&px=MTY2NTQ

Going back to Intel G45 and newer graphics has been a "BSD ring buffer" for H.264 and VC1 VLD decoding. All hardware up to now has had one "Bit Stream Decoder" ring for video decoding, but with the high-end "GT3" graphics of Intel's upcoming Broadwell hardware will be two rings. Broadwell GT3 (the highest-end graphics) will have two independent decoder rings for processing video commands. For the upcoming CPUs featuring GT3 graphics, this should mean a faster and more pleasant video experience, particularly when dealing with multiple video decoding streams.
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Assuming that GT3 has everything doubled in Broadwell it's no surprise. In Haswell GT3 the non-slice parts weren't doubled including the Media Engine. With Broadwell by the looks of it it's a true doubling this time. This should give Broadwell GT3 a huge transcoding boost in general over GT2.
 
Interesting that there is no mention of Carrizo in AMD's latest roadmap. I wonder if it been cancelled, or perhaps this particular roadmap is only designed to highlight their 'ambidextrous' strategy.

Screen-Shot-2014-05-05-at-2.44.00-PM-640x358.jpg
 
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