The PCI Express complex reveals another tradeoff AMD had to make. Unless there is a mistake in the document due to it's early state, AMD considerably reduced the amount of available PCIe lanes, from 24 total to 16 total. The discrete graphics connectivity only features 8 lanes that can be split into two x4 links. The general purpose core features 4 lanes that can be split into up to four x1 links, two x2 links, a combination of x1 and x2 links or a single x4 link. On the desktop version four additional lanes are available for the UMI interface to the FCH. On the BGA versions these lanes are not available, as the internal FCH is connected to these ports. It is unclear yet, why the graphics connectivity was chopped down and it is an aspect I will try to shed some light on at a later date.