Fall Processor Forum

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Fall Processor Forum starts from 10/24. The sessions that are probably interesting are

Oct. 25
"Application Customized CPU Design for Microsoft XBOX 360"
presented by Jeff Brown, IBM Distinguished Engineer, IBM Corporation
The previous presentation about the CPU was in Hot Chips and it was given by Microsoft as a session about the whole Xbox 360 architecture. This presentation by IBM may bring some new info.

Oct. 26
"Design Considerations for the Cell Processor"
presented by Alex Chow, Manager, S-T-I Design Center and David Krolak, Development Engineer, IBM
This is about software development for Cell. Probably FFT redux.
 
From that article
features 165 million transistors and is fabricated using IBM's 90 nanometer Silicon on Insulator (SOI) technology to reduce heat and improve performance. The chip's innovative 21.6 GB/s Front Side Bus (FSB) Architecture was customized to meet the demanding throughput and latency requirements of the Xbox 360 gaming platform software.

Is this the first time transistor count for XeCPU has been mentioned? I was thinking how that compared to Cell (234 million) as to how power use, cost etc. might compare, but being totally different designs I'm not sure that comparison is mouch use. Save at 70% of the size, it should be roughly 70% the cost :???:
 
> "Is this the first time transistor count for XeCPU has been mentioned?"

No, it's been mentioned before.

> "Save at 70% of the size, it should be roughly 70% the cost"

Die size/transistor count is important, but CELL is also trying to improve yields by negating a single SPE per die (21 million transistors), and yield issues also have to take into account the design process at Sony/Toshiba's semiconductor factories, and IBM's factories. They are a lot of factors that can affect yield, as I'm sure others here can explain better.
 
The disabled SPE transistor count ~ 21 mil, shouldn't be counted towards PS3 CELL, IMO. Though which version of CELL, DD1 ~ 234 mil or DD2 ~ 250 mil haven't been disclosed yet...
 
It's got to be DD2 - I don't even think DD1 has or will ever enter mass production. Plus, I think DD2 is the core revision that lines up with Sony's stated Flop-counts at E3.

And beyond just transistor-counts, we have to remember that transistor counts - even on the same process - don't always give the exact scaling in terms of transistor:die size. The SPE's in particular I'm pretty sure have a different average density than the PPE cores, though I have no idea what exactly those differences would be.

I would definitely like to know the XeCPU's exact die size though. :)
 
Shifty Geezer said:
From that article


Is this the first time transistor count for XeCPU has been mentioned? I was thinking how that compared to Cell (234 million) as to how power use, cost etc. might compare, but being totally different designs I'm not sure that comparison is mouch use. Save at 70% of the size, it should be roughly 70% the cost :???:
Well according to this Hot Chips 17 report by H. Goto about Xbox 360 CPU (165 mil trans.) / GPU, in the latest paper in August Cell processor is now 241 million trans. / 235 mm2 die-size.

EDIT: Also, with leaked Xbox 360 matherboard pics, Goto predicted the 5.4Gbps per-pin new FSB technology which is mentioned in the IBM PR.
 
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http://blogs.mercurynews.com/aei/2005/10/ibm_describes_x.html
Microsoft chip veterans Larry Yang, Jeff Andrews and Nick Baker -- former 3DO hardware engineers who joined Microsoft through the WebTV acquisition -- told IBM exactly what they needed the chip to do. In fact, that's why IBM's top engineer on the project is considered the "chief engineer," while Micrsooft's Jeff Andrews is considered the chief architect.
IBM's team implemented the design and finished it around 14 months after signing the contract.
Because Microsoft had a tight schedule, IBM did some unusual things. It undertook many of the verification tasks in parallel. Normally, such tasks are done one by one to ensure an easier debugging process. But the engineers didn't have that luxury. They relied heavily on simulation tools to debug various parts of the chip all at once. That helped them catch errors early on. The result showed that it worked. The chip was working within 24 hours from coming back from the factory. Within 48 hours, it was playing game code.
I remember someone in this forum pointed out when the Xbox 360 patent appeared that those guys on the patent had been behind 3DO M2, which sports dual PowerPC processors, I wonder what they were thinking back in they days when MS went to Intel for Xbox 1? My guess is the original hardcore-gamer-type Xbox team was defeated in corporate politics and those 3DO/WebTV guys resurfaced instead with a new chance.
 
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Good find One! :)

It really was a lightening-fast turnaround for that chip.

I'm also glad that the article reaffirms the corporate firewalls that were in place during the development for all three companies' chips; I've been wondering what the deal is with these PPE similarities, and I'm hoping it was parrallel development on the part of these teams rather than some 'chosen' core that IBM higher-ups decided to hawk to both teams.
 
So if IBM can get such a fast turn around by running QA in parallel, why don't they do this already? Will this reprsent a shift as the company finds it can halve design times by designing in the same way, parallelising QA testing? Or were MS just lucky that IBM got it right first time and there could have been big problems?
 
xbdestroya said:
It's got to be DD2 - I don't even think DD1 has or will ever enter mass production. Plus, I think DD2 is the core revision that lines up with Sony's stated Flop-counts at E3.
...

I agree, the DD2 is the most likely. Though I'm not sure about the flop-counts. The PPE is rated at 12 flops/cycle, 8 from the VMX units is a given but 4 is likely from the FPU acting as 2-way SIMD and MAD capable...or it could be a 2nd VMX unit but not MAD capable...
 
http://www.channelregister.co.uk/2005/10/25/ibm_xbox_ms/
The rather fancy, custom chip boasts three processor cores each running at 3.2GHz. The cores, based on the PowerPC design, connect into a shared 1MB L2 cache. Overall, the chip has 165m transistors, takes up 168 sq. mm of space and was built with a 90nm manufacturing process.
Brown refused to disclose the code-name of the processor or to say how much power it consumed.
What we've learned so far is that the code-name is Waternoose or PX and the power consumption is 110W...
 
Shifty Geezer said:
Will this reprsent a shift as the company finds it can halve design times by designing in the same way, parallelising QA testing? Or were MS just lucky that IBM got it right first time and there could have been big problems?
Part of the speed which the chip was built at is most likely due to each core essentially being the same as the PPE in Cell (probably a big part too). Shared workload means faster development...
 
Guden Oden said:
Part of the speed which the chip was built at is most likely due to each core essentially being the same as the PPE in Cell (probably a big part too). Shared workload means faster development...

What shared workload though?

Granted, there were a dozen or so Microsoft folks and maybe 400 IBM engineers in seven locations. IBM had other engineers working with Sony and Nintendo. But those engineers weren't allowed to talk. Spillinger said his IBM badge wouldn't even work in locations where Sony and Nintendo work was being done at IBM.
 
Also the PPE in DD1 is fairly different from the PPE in DD2 that was taped out at the end of 2004 and is similar to Xbox 360 CPU core.
 
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