Details on the new Toshiba fab in Oita

[V3]

That Forum was from 29th to 2nd. It should be over by now. Anyone find anything on that one ?

 

[V3]

No luck

But found this instead.

From the other thread

Gubbi wrote,

I'm fairly confident that this DRAM density is for a dedicated DRAM process (stacked capacitor) and not a logic process (trench capacitor).

http://www.eetimes.com/story/OEG20030421S0071

With the shift to 90 nm, the embedded DRAM structure will change to a trench capacitor type from the stacked capacitor structure.

So there you go Gubbi, its trench capacitor they are using from 90nm and on.

So those eDRAM going going to be densed.

 

[Vince]

So those eDRAM going going to be densed.

Yes, a bit denser than what Gubbi stated. IBM was claiming 25% smaller cell size compared to a conventional folded bit line considering an equivalent lithography process.

 

[Panajev2001a]

Well... why should we care about the 90 nm figure and guess the Cell size...


Hehe, seriously thanks for the link V3...

We have more info here:

http://www.sony.net/SonyInfo/News/Press/200212/02-1203E/

Embedded DRAM cell:
High-speed data processing requires a single-chip solution integrating a microprocessor and embedded large volume memory. Toshiba is the only semiconductor vendor able to offer commercial trench-capacitor DRAM technology for 90nm-generation DRAM-embedded System LSI. Toshiba and Sony have utilized 65nm process to technology to fabricate an embedded DRAM with a cell size of 0.11um2, the world's smallest, which will allow DRAM with a capacity of more than 256Mbit to be integrated on a single chip.

 

[V3]

Yeah, I am still wondering if anyone find anything on Toshiba bit from that Embedded Forum.

 

[megadrive0088]

what should be the standard res next generation, 720p? 1024i, 1024p?

 

[Panajev2001a]

http://www.mepcore.com/english

 

[Panajev2001a]

http://www.mepcore.com/english/frameset2_e.html


No this is not Cell based... Well Toshiba is Japanese 1st semiconductor company so it is natural they have several projects running in their R&D pipeline

 

[Gubbi]

Trench capacitors uses a horizontal (trench) structure, stacked a vertical.

So density will be worse

Cheers
Gubbi

 

[Gubbi]

We already debunked eDRAM density in that other PS 3 thread (can't be bothered to look up which one).

SONY and Toshiba are colaborating on process, no?

at 0.11um Toshiba has 35% worse density than IBM has at 0.13um (both trench capacitor eDRAM)

Cheers
Gubbi

 

[Panajev2001a]

Embedded DRAM cell:
High-speed data processing requires a single-chip solution integrating a microprocessor and embedded large volume memory. Toshiba is the only semiconductor vendor able to offer commercial trench-capacitor DRAM technology for 90nm-generation DRAM-embedded System LSI. Toshiba and Sony have utilized 65nm process to technology to fabricate an embedded DRAM with a cell size of 0.11um2, the world's smallest, which will allow DRAM with a capacity of more than 256Mbit to be integrated on a single chip.

Things have changed Gubbi

 

[nonamer]

Hey, look what I found:
http://www.eetimes.com/story/OEG20011016S0099

 

[Paul]

Interesting article you found.

 

[Vince]

Trench capacitors uses a horizontal (trench) structure, stacked a vertical.

So density will be worse

Even when using vertical transistors (eg. When there's no area penatly)? IIRC, IBM claims a net gain in aggregate area aswell as the advantages relating to 'soft errors'.

EDIT:

There are two basic camps today on how this can be done. IBM and Infineon advocate the trench capacitor approach, and the rest of the DRAM industry is by and large looking for ways to build a better stacked capacitor.

The vertical transistor DRAM cell developed by IBM and Infineon is an extension of the trench capacitor structure buried in silicon that was developed earlier this decade by IBM, Infineon and Toshiba. The trench capacitor structure situates the transistor on top of the silicon surface and to the side of the capacitor, but the vertical transistor is different in that it is buried inside the walls of the capacitor.

A main advantage of the IBM-Infineon approach is its reduction in the size of the cell relative to the lithographic feature sized employed. Today, manufacturers are generally able to construct DRAM cells that are eight times the employed feature size squared (8F2). IBM claims it can reduce the cell size to 6F2 -- a 25% reduction compared to a traditional "folded bit line" structure -- using the same process technology. http://www.siliconstrategies.com/story/OEG19991028S0040