The proprietary instruction set architecture (ISA) consists of about 60 instruction types, and follows a 3-operand, load/store RISC design. The decision of using a new simplified ISA bears on the goal of a simpler de-sign. For designing the Cyclops ISA we selected the most widely used instructions in the PowerPC architecture. In-structions were added to enable multithreaded functionality, such as atomic memory operations and synchronizationinstructions.
We evaluate a design with the following characteristics:128 thread units, each unit containing a register file (64 32- bit single precision registers, that can be paired for dou-ble precision operations), a program counter, a fixed point ALU, and a sequencer. The thread units are very simplecomputing processors that execute instructions in program order (completion may be out-of-order). Most instructionsexecute in one cycle. Each thread can issue an instruction at every cycle, if resources are available and there are nodependences with previous instructions. If two threads try to issue instructions using the same shared resource, onethread is selected as winner in a round-robin scheme to prevent starvation. If an instruction cannot be issued, thethread unit stalls until all resources become available, either through the completion of previously issued instructions, orthrough the release of resources held by other threads.
Groups of four thread units form a quad. The threads ina quad share a floating-point unit (FPU) and a data cache. Only the threads within a quad can use that quad's FPU,while any thread can access data stored in any of the data caches. The memory hierarchy has non-uniform access la-tencies. Thus, threads have faster access to their local data cache than to a remote cache. The floating-point unit con-sists of three functional units: an adder, a multiplier, and a divide and square root unit. Threads can dispatch a floatingpoint addition and a floating point multiplication at every cycle. The FPU can complete a floating point multiply-add (FMA) every cycle. With a clock cycle of 500 MHz, in :18_m CMOS technology, it achieves a peak perfor-mance of 1 GFlops per FPU, for a total chip performance of 32 GFlops.
