CPUs...why not more exectution units over cores?

[Gubbi]

Am I the only one who don't like code passing arrays as pointers

Either do

*a++=*b++ + *c++;

Or pass a[],b[],c[] to the function (arrays don't partial alias in C++)

Cheers

 

[Simon F]

(I thought already we went over this a few months ago. )

We did... but i can't seem to find it!

Am I the only one who don't like code passing arrays as pointers

Either do

*a++=*b++ + *c++;

No don't! Use an index which you update only once per iteration. Most CPUs have the ability to index relative to a pointer so incrementing 3 pointers per loop is often a bad idea (apart from the code being bloody hard to read!)

 

[MfA]

The only realistic alternative to multithreading for very wide issue processors is good old vector processing. Most of the time parallelism suited for a vector processor is just as suited for a multithreaded one though, but not vice versa.

 

[Gubbi]

No don't! Use an index which you update only once per iteration. Most CPUs have the ability to index relative to a pointer so incrementing 3 pointers per loop is often a bad idea (apart from the code being bloody hard to read!)

I'd expect a compiler to sort that out for you, but fair enough, do a

*(a+i)=*(b+i)+*(c+i)

My point was that pointers and array descriptors has different semantics.

Cheers
Gubbi

 

[Simon F]

The only realistic alternative to multithreading for very wide issue processors is good old vector processing. Most of the time parallelism suited for a vector processor is just as suited for a multithreaded one though, but not vice versa.

Perhaps what we need is a multi-threaded, VLIW vector processor

 

[MfA]

For a floating point processor with a fair bit of cache I dont think VLIW makes much sense. Dual issue with SIMD is the sweetspot IMO. With control circuitry already being a very small factor you might as well stay with superscalar.

 

[psurge]

The wave-scalar architecure is also quite interesting (a tagged-token dataflow architecture with support for multi-threading). See

http://wavescalar.cs.washington.edu/index.html

paritcularly:

http://wavescalar.cs.washington.edu/TR-2004-11-02.pdf

They report IPC ranging from 100+ for hand coded data-flow kernels (based on a synthesizable RTL model and cycle accurate simulators) to 1-2 on Spec2000.