Cell chip also gets around process problems by design
Easy to overlook in all the fuss about how the IBM-Sony-Toshiba Cell chip will challenge Intel is just how much performance improvement the radical new architecture also gets from some pretty mainstream process technology.
To ramp the blazing 4GHz, 256Gflop, low-power (48W) processor quickly to volume production, the companies opted for a 90nm process, not 65nm. The exotic raised transistor structures and more extreme spun-on low-k dielectrics originally considered got dropped along the way in favor of processes already up and working. Both the 90nm and the 65nm version will use mainstream CVD SiOC, with a k value of about 3, according to Sony semiconductor technology executives interviewed by WaferNews’ Japanese partner Nikkei Microdevices. The only process change planned for the 65nm version is reportedly to change the silicide from CoSi2 to NiSi.
Kenshi Manabe, Sony’s CTO for semiconductors, told Nikkei Microdevices that Sony will use the same production processes for the Cell chip as for its next-generation conventional embedded DRAM graphics chip for the PlayStation 2, at both transistor and interconnect levels. They will be made in the same Nagasaki fab, though the Cell chip is on silicon-on-insulator (SOI) and the other on bulk silicon.
Much emphasis was put on design-for-manufacturability from the beginning, by designing for the most effective optical proximity correction and doubling the vias to make sure one of them works. The other major changes to get the most performance improvement for the fewest manufacturing problems are SOI and strained silicon. “If we were going to increase operating frequency, not using SOI was not an option,†explained Manabe. He said that after testing both bonded and implanted SOI wafers, they found essentially no difference in either cost or yield. They used a partially depleted SOI, because keeping the Si layer completely uniform across the 300mm wafer in the fully depleted version, as required to maintain a stable threshold voltage, turned out to be too costly and complicated.
The Cell chip uses what developers argue is a relatively simple approach to create strained silicon as well, eliminating the epitaxial SiGe some others have used to create localized compressive strain on the pMOS. Instead, they use the dual stress liner system, depositing a highly tensile SiN cap layer over the whole wafer, then patterning and etching it away in pMOS regions, leaving tensile strain in the nMOS areas. Then they repeat the process with a highly compressive SiN cap layer over the wafer, and leave it only on the pMOS regions for compressive strain. With an off-current of 100nA/µm, this dual stress liner strained silicon improved the nMOS drive current by 11% and the pMOS by 20%. A microprocessor made with the technology and IBM’s Power Architecture design showed a 7% increase in operating frequency compared to other strained silicon technologies, and similar results are expected from the Cell chip. - P.D.