Correlation: Working ALUs and speed in NVG8x

[chavvdarrr]

http://www.ixbt.com/video3/g80_units.shtml
enjoy

 

[ChrisRay]

Now I cant read the website. Am I to assume that TMUs/ROPS are being scaled with these streaming processors?

 

[Sinistar]

They are using Rivatuner to disable blocks of ALU's. Does this disable the TMU also?

 

[ChrisRay]

I didnt know that rivatuner supported disabling of SP Cluster. I guess an easy way to check this would be to run a basic fillrate benchmark. I'll certainly try it out. Unless of course this is beta river tuner.

 

[Sinistar]

Im sorry, it actually says that they do it with tools from the guy who programs Rivatuner.

 

[trinibwoy]

They are using Rivatuner to disable blocks of ALU's. Does this disable the TMU also?

Does it matter whether they're disabled? The active ALU's won't be able to use the TMU's assigned to the inactive ones anyway right?

 

[Arnold Beckenbauer]

They are using Rivatuner to disable blocks of ALU's. Does this disable the TMU also?

Yes.:smile:

 

[ChrisRay]

Thats what I thought. The tests are interesting but not really surprising since SP/TMUs have ties to function. So the performance scales down relatively linearly.

 

[Pete]

Google translation.

I'm under the impression that NV40's ROPs were independent from the rest of the GPU. Is that still the case with G80? Is it packing shader/texture blocks and ROP/MC blocks, or just shader/texture/ROP/MC blocks?

I'm thinking split blocks (still hung up on NV40's crossbar, I guess), so that would lead me to believe these #s may point to ROP limits in certain games. Well, if we can overlook the potential CPU limits (12x9 1x1 with a 4600+, hmmm).

 

[Novum]

On G80 ROPs and memory partitions are combined. So there is no crossbare between the memory controller and the ROPs anymore.

 

[Pete]

Wait, there was a crossbar b/w the ROPs and the memory controllers? I never really gave that much thought with that generation, but I was assuming NV4x had the same ROP-MC integration as G8x appears to have. I meant b/w the pixel shaders (with their integrated TMUs) and the ROPs (e.g., the 6800's 12 pixel shaders but 16 ROPs): the "fragment crossbar" in NV's image.

 

[Demirug]

The NV4x version of the crossbar was a one way connection. The shader units send down the fragments to the ROPs. The ROPs then were connected to the second crossbar that was responsible for the memory access.

The G8x crossbar is now a two way connection. The next logical step would be making the texture units working in two directions too. This would allow to kick out most of the fixed function ROP logic and use the transistors for other things.