Complete Details on Xenos from E3 private showing!
- Thread starter dukmahsik
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I believe so, and for that they may well be stinky idiots as I think MS are for bandying this number. But I didn't understand that number back then, and don't yet know how relevant it is coz I don't know PS2's architecture too well.
Because you're just wrong. Sony claimed a 40GB/s (38.4 GB/s to be exact) bandwidth from the GS to the eDRAM AFAIK, you seem to be saying that Sony claimed it was from the EE to the GS. Sony says the BW between the EE and GS is 1.2 GB/s. MS is claiming it's from the GPU to the eDRAM which it isn't (it's only 32GB/s, or at least that's the number being thrown around).
Johnny_Physics
Newcomer
PC-Engine said:
I'm just guessing here: because it's wrong?
Two wrongs don't make a right, no matter how much you goose it, tweak it, spin it and reverse it
According to other more learned people than myself, the bandwidth between the GPU and eDRAM is 32GB/s and the bandwidth between the eDRAM and the logic located on the same chip is 256 GB/s. So the comparable numbers would be the 32GB/s on the 360 and the 38.4 GB/s on the PS2.
Because, if I understand right, the logic that processed the data held in eDRAM was on the GS. The GS had to fetch and store data across that bandwidth, so was limited to 48GB/s or whatever the figure is.PC-Engine said:
The Xenos figure though is for logic on the same chip as the eDRAM. The eDRAM is in essence a big level 1 cache. Since when have bandwidth figures for level 1 caches been used to describe system bandwidth?
My new thread on this, describing the Xenos as having a seperate processing unit, explains my understanding, but basically there two chips on the Xenos and MS have quoted the internal data access rate of one chip as bandwidth, whereas bandwidth is used to describe data transfer rates between different sets of logic and storage.
They could have reached the same with far less than 256GB/s. But quite likely it's just cheaper to implement an ultra-wide bus inside a chip than to implement compression. And at the same time, 256GB/s sounds great for marketing.Jawed said:
When you see the 256GB/s figure, and then look at the peak output figures, they seem surprisingly low, almost underwhelming.
But I think we're at some kind of turning point here. Comparing R500 and NV40 theoretical peak output capabilities you will notice R500 beating NV40 in just a single case - 4xAA with Z/stencil only. But this, along with blending which is also fast, is the most important case because that's single-cycle. When you have long shaders, peak output doesn't matter any more, fast fill is just for the shaderless stuff. Even for a relatively short shader with a trilinear anisotropic texture fetch, pixel output limits are hardly an issue. I guess that distinction will become really obvious with all the next-gen GPUs.
Current reports seem to imply that.PC-Engine said:
Sony claimed EE <-> GS bw is 1.2 GBytes/s and internal GS bw from/to edram was 48 Gbytes/s, there's nothing wrong with those numbers, this was crystal clear from day one.
I haven't anything against MS claiming edram INTERNAL bw is 256 GBytes/s
Jawed
Legend
X850XTPE's ROPS only have access to 37.6GB/s of bandwidth (actually, much less due to texturing), hence even at 1024x768 X850XTPE can easily see 20% FPS cost with 4xAA.
Next gen games don't just have longer shaders, they also produce more polys. So while the former won't soak up bandwidth directly (except if they use rendering to targets and dependent texturing) the later is a direct bandwidth cost.
Jawed
Next gen games don't just have longer shaders, they also produce more polys. So while the former won't soak up bandwidth directly (except if they use rendering to targets and dependent texturing) the later is a direct bandwidth cost.
Jawed
nAo said:
Ok let me answer try to justify MS's claim in the form of a question.
Lets say you split the chips one with vertex shaders for T&L and one for the pixel shaders, if the second one had EDRAM would youy quibble about the available bandwidth?
All ATI has done is split the chip later in the pipeline, just be for the AA expansion, Z Logic and the ROPS. They split it there because there is less info to pass backwards and forwards, the fact remains the ZUinits and ROPS have a real 256 Megabytes/second bandwidth available.
Yes there is a bus between the two chips that is less than 256 MBytes, but that would be true of a chip that split out vertex work.