Actually at least old radeons (r100, r200) support 32bit z buffers (even 3 formats, 32bit int z, 32bit float z, 32bit float w) in hardware (judging by the register bits). Not sure how much of that is exposed through the driver (or if it actually has higher precision than the 24bit formats). The obvious limitation is that depth + stencil is crammed together into 32bit, so 32bit z -> no stencil (which is also the reason the 16bit depth formats can have no stencil buffer).
Doesn't look like it was a feature really used...