Calculating memory bandwidth

[Bigus Dickus]

After seeing calculations done here and everywhere, I have a couple of questions.

This is my understanding of bandiwidth calculation, using 100MHz SDRAM as an easy example:

Clockspeed * bus width = bits per second, bits per second/8 bytes per bit = bytes per second.

So, for 100MHz SDRAM on a 128-bit bus, this gives: (100e6 cycles/sec * 128-bit) / 8 bytes/bit = 1.6 million bytes per second.

Now, this is where I'm a little confused. It seems common practice to call this 1.6 GB/s, but I was under the impression that 1024 bytes = 1 kilobyte, 1024 kilobytes = 1 megabyte, etc. Therefore, the 100MHz SDRAM on 128-bit bus would give 1.5 GB/s, not 1.6 GB/s.

I noticed in a calculation Tom Pabst made that he specifically noted using 1024 megabytes = 1 gigabyte, but he neglected all the 1024's when converting B to KB to MB, using 1000 instead.

So, what websites are correct? Are they all using a standard way of calculating memory bandwidth? Is it really correct to say that 100 MHz = 100 Mcycles/second = 100 Mbits/second = 12.5 MB/second instead of 100,000,000 bits/second = 97656 kilobits/second = 95.4 megabits/second = 11.9 MB/second? I would think the latter is the correct way of doing it.

So, if the R300 uses 620 MHz memory on a 256-bit bus, is it:

(620 Megahertz * 256) / 8 = 19840 MB/s = 19.8 GB/second

(620 Megahertz * 256) / 8 = 19840 MB/s, 19840 MB/s / 1024 = 19.4 GB/s (Tom's method)

[(620 Megahertz * 256) / 8 ] / 1024*1024*1024 = 18.5 GB/s (my method)



Second question: what actual clock speed is DDR-II 1GHz running? From reading several technical descriptions, it seems that DDR-II actually doubles fetch size to 4 bytes instead of 2, and has twice the bandidth per pin as standard DDR memory. It also seems accepted that DDR 400 and DDR-II 400 have the same bandwidth. This would lead to the conclusion that DDR-II 400 is runnin an actual clock of 100 MHz. This would make DDR-II 1GHz an actual clock of 250 MHz.

It seems rather common for people to refer to DDR-II as being equivalent to DDR but retooled to run at higher clockspeeds. I find this to be rather misleading, unless I am simply misinformed. It is running at a higher effective clock, due to the doubling of bandwidth per pin, but running at a slower actual clock. Yes, this does have the effect of making it easier to reach higher effective clocks due to the lower actual speed required, but I don't think that = retooled to run at a higher clock. It is retooled to double bandwidth at an equivalent clock, and initial offerings are clocked below DDR.

Or have I really missed something vital here?

 

[KimB]

So, for 100MHz SDRAM on a 128-bit bus, this gives: (100e6 cycles/sec * 128-bit) / 8 bytes/bit = 1.6 million bytes per second.

Look again. It's 1.6 billion.

Anyway, yes, there are two ways of defining KB, MB, GB, etc. It is standard practice for all memory storage to report memory sizes using the 1024 bytes/KB method. This was set long ago because 1024 is 2^10, and it is therefore trivial for the computer to report how many KB, MB, GB, etc. are available (whereas to calculated these in steps of 1000 would actually require math...I guess it was just a way to cut down on a few cycles...plus, it turns out it's more accurate since RAM always holds powers of 2 sizes).

Sometimes, the 1024 multiple are dubbed KiB, MiB, GiB, etc. to avoid confusion.

I'm pretty sure that signalling usually uses the 1000/prefix standard.

 

[Crusher]

The third calculation is the most "correct" of the three, since 1 MHz = 1,000,000 Hz and 1 GB = 1,073,741,824 (2^30) Bytes. However, it's still not right since the Radeon 9700 doesn't have 620 MHz DDR, it's 310 MHz DDR. The 620 MHz figure is related to the bit rate (but it is NOT the bit rate itself), and used simply to compare DDR to regular SDRAM. Two types of memory can have the same bandwidth, but completely different bit rates, depending on what kind of encoding they do.

The correct formula would be:

((310,000,000 Hz * 256 bit wide bus * 2 ) / 8 bits per Byte ) / 1,073,741,824 Bytes per GB = ~18.477 GB/sec bit rate

I haven't looked at the DDRII spec and don't know a whole lot about it, so I won't speculate about what kind of bit rate it has.

 

[Bigus Dickus]

So, for 100MHz SDRAM on a 128-bit bus, this gives: (100e6 cycles/sec * 128-bit) / 8 bytes/bit = 1.6 million bytes per second.

Look again. It's 1.6 billion.

DOH! silly mistake.

Anyway, yes, there are two ways of defining KB, MB, GB, etc. It is standard practice for all memory storage to report memory sizes using the 1024 bytes/KB method...

Sometimes, the 1024 multiple are dubbed KiB, MiB, GiB, etc. to avoid confusion.

I'm pretty sure that signalling usually uses the 1000/prefix standard.

Hmm... so it is as mixed up as I suspected. Signaling uses the 1000/prefix standard? Then Tom was wrong to use 1024 for the last part of the conversion... but then again, he had to be wrong one one part or another. So, what actually does use 1024 now, just internal reporting? HDD manufacturers use 1000 to inflate their storage size, and if signaling uses 1000 then that covers all memory and busses.

Strange. So what does something like Sisoft Sandra use to report CPU memory bandwidth? When utilities report back on CPU and GPU bandwidth, are the results a little lower than what we expect because of these differences in prefix multipliers?

 

[Bigus Dickus]

However, it's still not right since the Radeon 9700 doesn't have 620 MHz DDR, it's 310 MHz DDR.

I never said 620 Mhz DDR, I simply said 620 MHz.

The correct formula would be:

((310,000,000 Hz * 256 bit wide bus * 2 ) / 8 bits per Byte ) / 1,073,741,824 Bytes per GB = ~18.477 GB/sec bit rate.

Your (310,000,000 Hz * 256 bit wide bus * 2 ) is equivalent to my (620 Megahertz * 256). I am referring to the effective clock, you are using the actual clock and DDR signaling (*2). They are numerically the same, which is why my result is the same as yours. As far as I'm concerned, the two ways of referring to DDR speeds are interchangeable, depending on your point of view.

 

[Crusher]

From my point of view, if someone tries to sell me DDR running at 310 MHz, and they call it 620 MHz, they're wrong If you use them interchangably, the number itself loses meaning and the context its used in becomes extremely important.

Anyway, I guess I didn't mean to say your formula was incorrect, just that it doesn't seem consistent to use 620 MHz when you've factored everything else out.

 

[Neeyik]

From my point of view, if someone tries to sell me DDR running at 310 MHz, and they call it 620 MHz, they're wrong If you use them interchangably, the number itself loses meaning and the context its used in becomes extremely important.

Why is it wrong? In DDR-SDRAM, the data transfer points are latched on the changing voltage of the timing signal, not the steady state. That means in the period of one timing signal clock cycle you can have two latch points. Assuming that the RAM is capable of read/write every latch point that must surely mean it "runs" at the DDR speed?

This is like saying AGP 2x data transfers don't run at 133MHz, or 4x transfer rate isn't 266MHz. For sure in reality you're not going to actually get a data transfer 266 million times per second (for obvious reasons) but the fact remains that the buffers and RAM must be capable of read/writes at that rate - otherwise there's no point in even having the DDR technology (or differential strobes in the case of AGP 4x) in the first place.

 

[Crusher]

I guess it depends on what you feel the frequency is actually referring to. The way I was taught was that it refers the frequency at which the clock signal changes. The term DDR used with that then signifies that it is capable of two operations per clock cycle. Thus, saying 620 MHz DDR sounds to me like a 620 MHz clock frequency with two operations per clock, which is incorrect. It should be 310 MHz DDR, which is equivalent to, but not the same as, SDRAM that is running at 620 MHz.

Also, anytime you use a size prefix in reference to memory, it is done using the base-2 definition of the prefixes. That is, 1 MB of RAM is 2^20 bytes, not 10^6 bytes. Therefore, it seems logical to me that when you talk about memory bandwidth, traveling on a bus whose width is a factor of 2, this definition should also be used. Typically the people who use the base-10 definitions for the prefixes are marketing people, and they care a great deal more about selling their product than being technically accurate.

 

[elimc]

Second question: what actual clock speed is DDR-II 1GHz running? From reading several technical descriptions, it seems that DDR-II actually doubles fetch size to 4 bytes instead of 2, and has twice the bandidth per pin as standard DDR memory. It also seems accepted that DDR 400 and DDR-II 400 have the same bandwidth. This would lead to the conclusion that DDR-II 400 is runnin an actual clock of 100 MHz. This would make DDR-II 1GHz an actual clock of 250 MHz.

DDRII @ 1GHz is actually running at 500MHz. DDRII @ 400MHz has an actual clock of 200MHz. The BW per pin is theoretically doubled, but I believe that fewer pins may be used. Plus, the BW per pin is not actually doubled; the memory array runs at only half speed.

 

[Bigus Dickus]

DDRII @ 1GHz is actually running at 500MHz. DDRII @ 400MHz has an actual clock of 200MHz. The BW per pin is theoretically doubled, but I believe that fewer pins may be used. Plus, the BW per pin is not actually doubled; the memory array runs at only half speed.

Really? I'm pretty sure in the spec sheets I read that the bandwidth per pin has been doubled over DDR. So they're using half the pins then?

If that's really true, then DDR-II is just retooled for higher clockspeeds, if using a 4 bit fetch with half the pins makes signaling easier at higher clock speeds than a 2 bit fetch with twice the pins.

Hmm... when doing bw calculations, its always clockspeed and bus width, plus any multipliers for DDR or QDR. I don't see how, if DDR-II is doubling the bits per pin transferred, that the bandwidth per clock isn't also doubled over that of DDR, given a certain bus width. Now, you can argue that DDR-II is designed to transfer the same bandwidth as DDR at the same clock speed, but using a bus half as wide. I might buy that. But in graphics cards, the bus is set by design at a certain width.

Does that mean, then, that DDR-II is offering twice the bandwidth per clock as DDR in graphics applications, where the bus width is held constant?

If the NV30 uses a 128-bit DDR-II bus, is that equivalent to a 128-bit DDR bus running at the same clock speed, or a 256-bit DDR bus running at the same clock speed? I was under the assumption that it was the former, but if DDR-II 1GHz is really running at an actual clock of 500MHz, and not at the 250 MHz I had thought, then I don't see how it could be.

Could someone please clarify this for me?

 

[KimB]

If the "bandwidth per pin has been doubled over DDR" it's probably more due to the increase in clock speed than just switching over to 4x signalling. This is probably referring to DDR II in comparison to DDR used for system memory.

 

[Xmas]

As for the prefixes, i'd really like to recommend the use of KiB, MiB or GiB for base-2 figures. You may not like these ones, but it's an easy way to avoid ambiguities.

 

[Bigus Dickus]

If the "bandwidth per pin has been doubled over DDR" it's probably more due to the increase in clock speed than just switching over to 4x signalling. This is probably referring to DDR II in comparison to DDR used for system memory.

After reading several more articles and tech reports, I think I'd have to agree. It's all pretty ambiguous, and I think at least a few of the sources I read are genuinely confused over what DDR-II entails. But, by taking the side of the majority, I think DDR-II really is only a clock speed increasing technology (with numerous other design changes from DDR, but none which directly affects bandwidth).

At least I can sleep easier knowing what to call DDR-II's clock speeds.

 

[elimc]

The data bus is still double pumped, but the memory array is multiplexed by four. The doubling per pin you are talking about probably refers to the memory array. Therefore, there data bus is the bottleneck right now because it is only double pumped.

The meory array BW per pin is doubled, allowing more headroom for clockspeeds. DDRII wouldn't be at 1GHz if it weren't for the memory array being multiplexed by four. Unfortunately, there is a slight latency increase with multiplexing and possibly more used up die space.

 

[KimB]

I'm curious to find out whether the 1GHz number is for parts designed to be used as system memory, or video memory.

After all, video memory's always had much higher clock speeds. It would make more sense for the 1GHz DDR II to be for video memory...

 

[Basic]

Yes Bigus, the final conclusion was right.
DDRII can be seen as a clock enhancing tech. There's some nicer things in the timings too, but data rate is 2x clock frequency, just as DDR. I can also give you a hint to quickly see if someone is just faking his knowledge about DRAM. If he talks about using QDR for main memory on a graphics card, then thats a sure sign that he doesn't know what he's talking about. (Just a pet peewee of mine. )


Now about the prefixes.
I agree fully with Xmas. The Ki/Mi/Gi prefixes are realy nice.
But they still don't work for the typical strange units for memory bandwidth. And people might think that you have some DVD piracy business if you say that you have 256 MiB in your PC.

Things were so much easier in the good old days when nobody even thougth about needing larger prefixes than 'K'. Then you knew that 1k = 1000, and 1K = "a large kilo" = 1024. Maybe we should go back to just use them. Then we could say things like:

I just bought a 80 kkkB harddisk.
I've got 256 KKB RAM in my computer.
And the tricky one:
A 128 bit DDR bus at 300 MHz can transfer 9.6 KkkB/s.

 

[OpenGL guy]

1K = "a large kilo"

Be careful! You'll have the DEA on your case if you keep going on about "kilos"

 

[elimc]

Did I do ok on my post Basic?

 

[Basic]

elimc:
Yes, you're right.

I'm assuming that you mean 'Bus Width' and not 'BandWidth' when you say 'BW'. And it's because the memory array is multiplexed by four that you get a minimal burst of four. I started to write a post earlier with some details of the internals (like the memory array multiplexing), but then I deleted it because I was afraid that I only would introduce one more factor of confusion.

But maybe it should be mentioned.
Let's think about a 32 bit DDRII-1000 chip.
It has a data rate of 1000Mb/s for each pin.
The clock frequency is 500MHz.
But the memory array (the core of the chp) gets 250M accesses per second.

What happens if you want to read a 4-burst of data?
You send an addres to the chip.
4x32=128 bit is read in parallel from the memory array.
That data is sent in 4 chunks, each 32 bit, one chunk at each clock edge over two (500MHz) clock cycles.


So datarate is 1000MHz, clock is 500MHz, and there's something internal in the chip that normally not needs mentioning that runs at 250MHz. Now forget about the 250MHz figure and think of DDRII as DDR at high clocks and with a minimum burst length of 4.

 

[elimc]

Actually, I did mean BandWidth.

And I was sooo close. Back to the books for me!