How dare you! [emoji23]
Baseless Next Generation Rumors with no Technical Merits [post E3 2019, pre GDC 2020] [XBSX, PS5]
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How dare you! [emoji23]
AbsoluteBeginner
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So apparently Komachi tweeted certain semi custom SOC has gone through E0 revision, which is admitedly alot. This matches AquariusZi's info from November of yet another revision of Oberon.
Was revision required because they added 50% more CUs, new memory controller to chip and RT or are they having an issue with getting such a high clocks working for acceptable amount of chips in waffer? Lets see, but AqauriusZi info about ~50mm² difference between the chips would lead me to believe its additional stepping related to very high clocks they are trying to hit.
I remember old Intel processor which went to G stepping, and these were same chips as earlier steppings, but could hit higher clocks at better thermals.
Was revision required because they added 50% more CUs, new memory controller to chip and RT or are they having an issue with getting such a high clocks working for acceptable amount of chips in waffer? Lets see, but AqauriusZi info about ~50mm² difference between the chips would lead me to believe its additional stepping related to very high clocks they are trying to hit.
I remember old Intel processor which went to G stepping, and these were same chips as earlier steppings, but could hit higher clocks at better thermals.
What happens at 5pm?
2pm is the AMD keynote? Phil was on last year, he may be back or at least drop some more details of how new AMD IP is powering Xbox.
Dam these conferences on the west coast, mumble GMT + 8
I doubt they have that much time to add so many things so i will go for solving high clocks issue, but who knows.
Apparently, twitter drama queens know how to attract lemmings of followers with their ever changing narratives and stories.
Who are you talking about?
AbsoluteBeginner
Regular
My own opinion in this baseless next gen rumor thread was always the same, MS likely made phenomenal decision on going dual SKU. Perhaps Sony looked into AMD's roadmap, looked into their BC method and said "We will need to go 36CU with very high clocks. That will be hard and we will have to have chip earlier then competition, but it will likely cost us millions to make sure yields of such high clocked chips are good."
Basically, Sony went with strategy that almost cannot be beaten with single SKU. Nothing MS did with single SKU would result in palpably better performance then PS5, because Sony already went to absolute limit and decided to use silicon as much as its possible. But, if they go with 2 SKUs and pretty much say "fuck the console factor" with 2nd one, then all bets are off. I personally think Sony were caught of guard and if it proves right, it will be interesting to hear a story of PS5 development.
Can you specify what did Komachi change about the narrative and story? We know Oberon had A0 and B0 steppings, we know (from AquariusZi), that Oberon is "one size smaller" then Arden and that its going through constant revisions. Now, if other, relatively reliable side (Komachi/Apisak) say its on E0 stepping, its very specific information. Its far cry from "My dad works at Nintendo..."
The narrative so far has nothing to do with MS outmanoeuvring Sony in regards hardware design and everything to do with Sony wanting BC as a priority and not having a good way to pull that off. No matter what MS do, that supposed PS5 solution would be the same.
I imagine an E0 stepping would still be related to bug fixes and not major hardware changes. Changing to a different memory controller, adding CU's, etc would be a huge undertaking and I'm not sure would constitute just a stepping revision, more likely a new SOC designation.
In theory, an SOC with a different stepping should be pin compatible and a drop in replacement. Messing with the external bus would not just impact the SOC but all the associated validation hardware and devkits. That seems too big of a change.
In theory, an SOC with a different stepping should be pin compatible and a drop in replacement. Messing with the external bus would not just impact the SOC but all the associated validation hardware and devkits. That seems too big of a change.
AbsoluteBeginner
Regular
In addition to what you said, Oberon chip is still rumored to be ~50mm2 smaller then Arden. This coming from Taiwanese forum poster AquariusZi who has history of incredibly good leaks on TSMC/AMD side. I imagine additional CUs would result in considerably bigger die, as well as perhaps wider bus.
Now, perhaps they said somewhere around summer they are going with 7nm EUV and will redesign chip and add more CUs/wider bus. Not exactly believable, but lets wait and see.
The bus doesn't need to be wider. MS has 560GB/s for 12Tf. They can have about the same bandwidth using a 256bit bus.
D
Deleted member 13524
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I think what this thread actually needs is another pastebin rumor.
11TF with 40 CUs would need 2150MHz core clock.
576GB/s would need 18Gbps chips.
2.5GB/s SSD would need... well, a regular old 4x NVMe PCIe 3.0 TLC model and not even a great one at that.
11TF with 40 CUs would need 2150MHz core clock.
576GB/s would need 18Gbps chips.
2.5GB/s SSD would need... well, a regular old 4x NVMe PCIe 3.0 TLC model and not even a great one at that.
Running PS4 Pro games at potentially 2.2x the framerate potentially without a single minute of software development efforts isn't a good way to pull BC off?
AbsoluteBeginner
Regular
MS has "theoretical" 560GB/s (in Github doc). They can comfortably go up to 720GB/s.
Ariel had theoretical BW of 448GB/s and then Oberon B0 had 530GB/s. Its simple memory clock upgrade on same bus. I doubt MS would go for 320bit bus just to go for fairly conservative memory speeds.
In any case, as far as Oberon goes, such stepping would indicate chip that is going through as many revisions to hit 2.0GHz clocks on good yields. I remember old Intels having up to G1 steppings. Same chips, same specs, up to 15-20% OC improvement on lower voltage.
Who knows, perhaps Navi 10 issue was lack od R&D and rush to get to market, and Sony decided to put alot of money into chip to get to these speeds - hence E0 stepping.
If anything,this only lends credence to Github leak with Oberon B0 being last stepping around May/June.
But few days ago 2.0GHz Navi made 0 sense, BC or not. If they can run any game at that clock, they will surely look to clock native chip near that frequency because it pretty much guarantees chip to be maximized completely.
Playing PS4Pro games on 36CUs at 2.0GHz, just to up CUs to 48-56CU at ~30% less clocks make no sense IMO.
Needs to be wider. MS is woefully insufficient I think at 560 GB/s
It should be mentioned that last Oberon revision in the github doc was B0(or was it b1?). If this is Oberon, and we're not 100% sure it is, C and D revs had to have happened, right? Could those 2 major revs be done between june and november of this year, or was the data in the github from june 2018 when the doc was 1st made?
Wasn't this the case? Isn't that why navi12 looks to be more efficient? -rogame suggested that navi12 is mostly bug/efficiency fixes that Amd skipped to get navi10 to market quicker.
AbsoluteBeginner
Regular
D
Deleted member 13524
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You mean like the exact course of action they took with the XBoneX, by launching a console with a 384bit bus using 6800MT/s GDDR5 when all midrange (and up) GPUs launched that year were using 8000MT/s GDDR5 or even 10 000MT/s GDDR5X?
It still doesn't, if your plan is to develop a RDNA GPU towards its optimum place within the power/frequency curve. Which is what the PS4 did with a 800MHz 18 CU GPU (when the HD7870 desktop equivalent was clocking at 1GHz) and the PS4 Pro did with a 911MHz 36 CU GPU (when the RX480 desktop counterpart was running at 1.25GHz).
But if in BC mode you can only use 36 CUs then the best plan would be to disable everything else and clock those 36 CUs as high as you possibly can within the same TDP.
Has anyone made an attempt to measure that?
AbsoluteBeginner
Regular
Looks pretty big and rectangular, but it might be the angle.
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