ATI Shader Event at London ?

[Scott_Arm]

Wha?

I thougth Verilog was havin a tough time against VHDL ... maybe not?

 

[sireric]

Don't let my long ears frighten you!.

Is this how you stop yourself from frightening people?

Thanks for making me smile!! I owe you one now!

NB: And I'm writing Verilog this morning, so I take partial offense at that!

Mmmm, now, what might that relate to? Care to give any details! [/quote]

In a few years, I'll let you see the results!

 

[sireric]

Re: Wha?

I thougth Verilog was havin a tough time against VHDL ... maybe not?

Actually, VHDL was used at ATI for quite a few things (Original Radeon and all the R2xx products). But since the R3xx, we've moved back to Verilog, and now are mostly verilog. From a CAD support sense, there's much more available for Verilog than VHDL. Simulators, formal checkers, etc... all work much better & faster in Verilog. And with SystemVerilog down the road & V2k now, it's not that bad and the futur is rosier.

 

[Scott_Arm]

Re: Wha?

I thougth Verilog was havin a tough time against VHDL ... maybe not?

Actually, VHDL was used at ATI for quite a few things (Original Radeon and all the R2xx products). But since the R3xx, we've moved back to Verilog, and now are mostly verilog. From a CAD support sense, there's much more available for Verilog than VHDL. Simulators, formal checkers, etc... all work much better & faster in Verilog. And with SystemVerilog down the road & V2k now, it's not that bad and the futur is rosier.

Cool for Verilog ... balls for me ... I'm just graduating from college with a pretty intensive course in VHDL under my belt. Our prof was convinced no one uses Verilog, so we never touched it.

 

[sireric]

Re: Wha?

I thougth Verilog was havin a tough time against VHDL ... maybe not?

Actually, VHDL was used at ATI for quite a few things (Original Radeon and all the R2xx products). But since the R3xx, we've moved back to Verilog, and now are mostly verilog. From a CAD support sense, there's much more available for Verilog than VHDL. Simulators, formal checkers, etc... all work much better & faster in Verilog. And with SystemVerilog down the road & V2k now, it's not that bad and the futur is rosier.

Cool for Verilog ... balls for me ... I'm just graduating from college with a pretty intensive course in VHDL under my belt. Our prof was convinced no one uses Verilog, so we never touched it.

A lot of colleges teach VHDL instead of Verilog. I think that the real reason is that there's more free tools for VHDL than Verilog. But for the ASIC industry in general, it's still mainly Verilog. Having said that, once you know one HDL, learning the other is pretty easy. In all the interviewing we do, we rarely would consider it a problem to not know Verilog if VHDL is known; at least straight out of college. GPA's, research, etc... are *much* more important

 

[Scott_Arm]

cool

From what I've seen, Verilog is C-like in appearance, which wouldn't be a problem for me at all.

 

[3dcgi]

VHDL still seems to be used in the defense industry and Verilog really is easy to learn if you already know VHDL. I found I could follow Verilog just fine even though I'd never read a book on it. I did have to read up just a little though to understand the finer details of blocking statements.

People often say Verilog is more C like than VHDL, but I just don't see it aside from comments being //. I really wish Verilog used {} instead of begin/end for blocks. Sorry... enough of my pet peeves.

 

[sireric]

VHDL still seems to be used in the defense industry and Verilog really is easy to learn if you already know VHDL. I found I could follow Verilog just fine even though I'd never read a book on it. I did have to read up just a little though to understand the finer details of blocking statements.

People often say Verilog is more C like than VHDL, but I just don't see it aside from comments being //. I really wish Verilog used {} instead of begin/end for blocks. Sorry... enough of my pet peeves.

If it bugs you that much, just write a little perl script and then use brackets

 

[gandalfthewhite]

i always thought sireeric was vulcan but tahs me

taht reminds me where ya been havent seen you around you know where lately.

it would be very interesting to see UNI shaders in R520 BUT i doubt it more likely just refering to the R500 chip

 

[2senile]

Saw some report on "Le Inq", including this curious statement:

All the hacks assembled in Vinopolis agreed that despite Valve and a big racket about Half Life 2, it was a very good event. Although we did capture a picture of Dave Baumann falling asleep during the proceedings.

Any rumours/gossip ?

He's a married man! It is very likely that it was an alcohol induced stupor rather than such a thing as simple sleep.

Sorry "Wavey", couldn't resist.