Did he note down the latency for reciprocal instructions (to do divides on the SPU) ?
Can he correct his first article on CELL as it gives the idea that SPU's are mostly FP processors with limited integer processing capabilities (like EE's VU's) ? SPU's ISA seems to have FP and Integer instructions (like an Integer and a Floating-Point MADD instruction) for both vectors and scalars (SPU's can do scalar and vector/SIMD processing from the presentations and the bits and pieces of SPU ISA SiBoy has posted here).
What about the presentation on the Double-Precision FP unit connected with CELL by IBM at ISSCC 2005 ?