ARS Technica: Introducing the Cell

Discussion in 'Console Technology' started by j^aws, Feb 8, 2005.

  1. j^aws

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  2. Titanio

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    Yes, interesting indeed.

    Although I'm confused slightly - if it's dual issue, does that not allow for out-of-order execution, even in a simple form?
     
  3. London-boy

    London-boy Shifty's daddy
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    I was gonna reply with a loud "NOOOOOOOOOO ANOTHER THREAD ON CELL!!!!!!!"... But that was quite interesting.
     
  4. Deepak

    Deepak B3D Yoddha
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    Damn, Jaws. I was about to post same article. :wink:
     
  5. Megadrive1988

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    I actually DID post a link to that article, twice. but then i had the thread one erased. all that remains is the link in one of the other Cell threads (forgot which one) probably ISSCC thread.

    edit: yup, here: http://www.beyond3d.com/forum/viewtopic.php?p=458721&highlight=21+million#458721

    8)

    but glad you made a thread out of this one Jaws. afterall, one can NEVER have too many Cell-threads. whoa i made a pun :lol:
     
  6. SiBoy

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    In this case, no. They opted for simplicity.
     
  7. j^aws

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    Some clarifications from the above article by the author Hannibal. His article is only 'Part 1' and more should follow as details emerge...
     
  8. j^aws

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  9. j^aws

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    [​IMG]

    Above is Xenon/ Xbox2 patent. Focus on the L2 cache...a bit of imagination needed, but the L2<>GPU sharing is similar to CELL below with it's L2 sharing...

    [​IMG]

    ...the CELLs PPE sharing it's L2 cache with 8 SPEs looks similar...and there was an IBM patent describing the above also.


    i.e.

    CPU<=>L2 Cache<=>GPU

    where,

    1 Xe CPU core >>> PPE,
    1 Xe GPU >>> 8 SPEs (R500 shading ALUs equivalent)

    Above is just an analogy but it's strikingly similar as suggested by some IBM patents! :D ;)
     
  10. marconelly!

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    Can someone give a link to that SCEE PDF that Hannibal talks about?
     
  11. one

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  12. j^aws

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    SPE's are essentially pixel shaders :?: What does this mean for the NV5x GPU :?:
     
  13. version

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    a pixelshaders on 4 GHZ , its fine
     
  14. nAo

    nAo Nutella Nutellae
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    IMHO, it means Hannibal is wrong ;)
     
  15. j^aws

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    Was it not expected that the SPEs in CELL be vertex shaders and the NV5x GPU would be the pixel shaders (and maybe vertex shaders also)?
     
  16. j^aws

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    You post there...go and tell him he's wrong! :p

    ...It's in the 'Part 1' thread... ;)
     
  17. version

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    possibility:

    1 . SPE in GPU
    2 . deferred rendering
    3. peer to peer
     
  18. Panajev2001a

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    I think Hannibal, with all due respect, is off when he says that SPE's are essentially Pixel Shaders like Wasson states.

    When people say that SPE's are not going to be used too much for rendering (although I can see a system doing software rendering, just not obtaining the speed a CELL CPU + nVIDIA GPU/ATI GPU can reach), they mean some specific portion of the rendering pipeline.

    You can use them as pixel shaders of course, you can get them to sample and filter textures: they just won't be as fast doing that as a dedicated multi-threaded ALU + close-by hardware Texture Management Units can be.
     
  19. akira888

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    EDIT3: Pana said it better above. :)
     
  20. j^aws

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    Okay... all your explanations sound plausible...but something smells fishy! :D
     
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