Great, thanks a lot!I think I edited it wrong at some point, corrected it.
Great, thanks a lot!I think I edited it wrong at some point, corrected it.
I agree although at least the extra registers of ARMv8 should help compared to ARMv7 or x86-64, right? Also an extra load unit might be difficult to feed from the L1 data cache - I'm not sure what trade-offs they are doing there in terms of bandwidth/banks/etc. given their huge 128KiB capacity.BTW I think that having two L/S ports is on the low side for a design that wide.
I was not thinking about having a third load, but rather being able to issue two loads and one store; that's useful for some computing tasks that stream their data (e.g., summing two vectors). IIRC Intel can do it since Haswell and their CPU are less wide.I agree although at least the extra registers of ARMv8 should help compared to ARMv7 or x86-64, right? Also an extra load unit might be difficult to feed from the L1 data cache - I'm not sure what trade-offs they are doing there in terms of bandwidth/banks/etc. given their huge 128KiB capacity.
Is there any benefit for a future A-series SoC to have "big" cores, out-of-order "little" cores, and a third tier of in-order tiny cores?Andrei Frumusanu said:What did surprise me a lot was seeing just how well Apple’s small cores compare to Arm’s Cortex-A73 under SPECint. Here Apple’s small cores almost match the performance of Arm’s high-performance cores from ust 2 years ago. In SPEC's integer workloads, A12 Tempest is nearly equivalent to a 2.1GHz A73.
However in the SPECfp workloads, the small cores aren’t competitive.
[…]
In recent years I’ve felt that Arm’s little core performance range has become insufficient in many workloads, and this may also be why we’re going to see a lot more three-tiered SoCs (such as the Kirin 980) in the coming future.
I was referring to the Android SoCs - the middle gap is now quite big. We'll see some interesting solutions in the next gen for this.AnandTech has released SPEC2006 estimates for the small CPU cores in the A11 and A12, as well as Neural Engine benchmarks.
Is there any benefit for a future A-series SoC to have "big" cores, out-of-order "little" cores, and a third tier of in-order tiny cores?
That's just some assumption, you can program PLLs with any frequency.All precise frequencies I measured on A7,A9,A11 are divisible by 24MHz. (So 1587 or 2083 are just not possible)
In theory, but we have frequency range/steps defined by Apple.That's just some assumption, you can program PLLs with any frequency.
Which predecessor? A10X or A12?Well, damn. They promise 35% higher single thread performance and over 90% better multithread over its predecessor
They compared to the A10x. Still have an aluminium body, which helps with heat dissipation, as opposed to the iPhones.Which predecessor? A10X or A12?
Nonetheless, it sounds like an impressive SoC. I wonder if it has the same 4*32bit channels. Using LPDDR4X 4266MT/s, they'd get almost 70GB/s total bandwidth. That's a lot more than a Geforce MX150 (GP108) GPU, and actually above the Xbone without the EDRAM.
dont worry based on the last half decade or so next years intel CPU will be another ~5% quickerWell, damn. They promise 35% higher single thread performance and over 90% better multithread over its predecessor
I guess no. It's quite close to my laptop i8650u which definitely has a fan or twoDoes any intel/AMD chip running without a fan match this chip?
Also, the previous generation 10.5" iPad Pro did not get a price drop as it is still $649.It’s already a $150 premium over last years model.