Oh we will. Andrei is having a field day here.
Apple A12, A12X, and A12Z SoCs
- Thread starter iMacmatician
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iMacmatician
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When can we expect to see the review?Oh we will. Andrei is having a field day here.
iPhone X already had enough RAM to run SPEC 2006 (64-bit SPEC 2006 needs up to 2GB for 64-bit environments). But isn't iOS limiting the quantity of RAM a process can use?
Nebuchadnezzar
Legend
I have full SPEC numbers from A9 to A12, minus MCF. MCF doesn't work without workload modification because the kernel memory allocator refuses to outright allocate a single huge 1.8GB chunk, even on the new 4GB phones.
When it's done.
AFAIK it’s not a hard coded limit, but when you run above certain percentage of the total amount of RAM (about 60%) your app will likely crash. So it’s possible to use up to about 2GB if you run it on an iPhone 8 Plus.
In terms of transmitting information, it’s mostly a boon that an aggregate score cannot be calculated, and the subtest results has to be considered instead.
Agreed but that was obviously not what I was pointing at. Any of it consists of 3rd party IP and is subject to royalties; beyond that remains to be seen if there's more to it on a hw level. One low level test that would interest me most is tessellation in gfxbench. The few results that appeared in the latter database point at a healthy performance difference compared to A11 in benchmarks that contain some portion of tessellation (car chase and newer....), but compared to A10X its more or less in the same ballpark.
Do you also have numbers for the X versions of the chips?
That's unfortunate, but having all the rest is already quite interesting!
Nebuchadnezzar
Legend
No.
A12 is quite a substantial upgrade over A11, didn't really expect it to be that big of a difference actually. The 50% uplift in GPU perf is quite conservative if anything. Not sure yet if that's because of better clock speed curve due to improved thermals/power consumption over A11.
I prefer to wait for the first reliable review(-s), before I'll personally jump to any preliminary conclusions.
Apple’s second generation neural network algorithm accelerator seems to be similar in class to PowerVR’s 2NX. I know they didn’t use Imgtec’s design for their processor, but that would’ve just been another synergy for them to bolster their processor design teams had they purchased Imgtec.
Still seems crazy to me the two companies couldn’t come to a deal for an acquisition considering how many other, comparatively arbitrary, processor design teams Apple picked up along the way while not closing the deal with their long-time partner who had world-class engineers in all the areas Apple needed from GPUs to CPUs, NNAs, ISPs, video cores, etc. Oh well.
Must have been some major falling out on the business side when they were interested in the acquisition.
Still seems crazy to me the two companies couldn’t come to a deal for an acquisition considering how many other, comparatively arbitrary, processor design teams Apple picked up along the way while not closing the deal with their long-time partner who had world-class engineers in all the areas Apple needed from GPUs to CPUs, NNAs, ISPs, video cores, etc. Oh well.
Must have been some major falling out on the business side when they were interested in the acquisition.
Or apple needed only engineers. Marketing, management, ip handling etc. parts would have been either destructive to apple culture or not needed. Bad pr and hurt feelings from ex imgtech employees after terminating all people, deals and offices not useful for apple would likely have been worse than doing internal development.
Worst case, apple would have taken pr and financial hit and engineers they tried to acquaire would have quit. It's better to grow organically based on need. Also imgtech clients might have sued apple once the deals start to be terminated. Apple likely had 0 need for imgtech ip licencing business.
Andrei article is up: https://www.anandtech.com/show/13392/the-iphone-xs-xs-max-review-unveiling-the-silicon-secrets
As always very interesting read!
@Nebuchadnezzar A quick question: you measured 2 LD and 2 ST per cycle. Did you try a mix? It could be that they have dedicated paths for LD and ST. For instance they could have 2 LD + 2 ST or 1 LD + 1 ST + 1 LD/ST.
As always very interesting read!
@Nebuchadnezzar A quick question: you measured 2 LD and 2 ST per cycle. Did you try a mix? It could be that they have dedicated paths for LD and ST. For instance they could have 2 LD + 2 ST or 1 LD + 1 ST + 1 LD/ST.
Nebuchadnezzar
Legend
They're two combined L/S ports, I mention it at the bottom the µarch page.
Then I find the wording in the article ambiguous:
That perhaps is just me, but I think saying "two load and store units" or "two load/store units" would be clearer
BTW I think that having two L/S ports is on the low side for a design that wide.
Nebuchadnezzar
Legend
I think I edited it wrong at some point, corrected it.Then I find the wording in the article ambiguous:
That perhaps is just me, but I think saying "two load and store units" or "two load/store units" would be clearer
BTW I think that having two L/S ports is on the low side for a design that wide.