another Dave Orton interview

[WaltC]

You're not the only one who's sighing. The thing is, i think the "Other things being equal" is an invalid statement. You must disagree with that and that's fine by me. We disagree.

Heh... You're right, other things aren't equal, like low-k, for instance, which I think was what Orton was talking about being surprised to see that nV40 wasn't using to achieve things like higher clocks and lower power consumption since, ostensibly, that's how ATi achieved them.

So Jen Hsun's talk about Ati handpicking boards for reviewers and such crap wasn't FUD either then, or ?

I mean, he don't know for certain but he had his suspicions.

And then I’ve heard some, tongue in cheek, talk that NVIDIA isn’t counting die-per-wafer, but wafers-per-die, and whenever this is the case you’ve certainly crossed a threshold!

(Emphasis mine)

In reading JHH's arcane and bizarre statements above as quoted by Dave B. in context, I am unable to find the words "tongue in cheek" anywhere. Could we therefore deduce from this that one statement is tongue in cheek and the other is not? Seems reasonable to me... (And that's what makes JHH's statement so frightening, isn't it, to think that he might actually think someone might believe it? Heh... OTOH, even though Orton's statement has a solid rational basis supporting it, he still calls it "tongue in cheek.") There's fud, and then there's FUD, isn't there?

 

[Sabastian]

I don't really understand your point, your are saying that it's already done on 3 sites for R600, i'm saying that R800 will be the first true unified chip with te 3 sites working on hand in hand together with the same workload dispatched.

From my little experience in organization consulting, only when the 3 sites are totally operational, we can talk of unified, before, it's just adjustment on the path to achieve the goal.

[action]shuffles crap out of the way on my desk[/action] WTF.. what do you call it when more then one organization works together on any project? A team effort... right? How else can they do that without coordinated work? If they are working in a coordinated manner then indeed they are unified.. That is the point. You can brood over that and be mystified about it for as long as you like but I am done talking about it.

 

[Dave Baumann]

I don't really understand your point, your are saying that it's already done on 3 sites for R600, i'm saying that R800 will be the first true unified chip with te 3 sites working on hand in hand together with the same workload dispatched.

You'll never have "the same workload dispatched" as there will always be different core elements of the teams inolved, for instance I'll wager that most of the silicon layout and implementation will come from the Valley, while all three sites will be working on the R&D that goes into the final silicon. Again, this is the case for R600 - all three sites have helped to develop it, in that technology that goes into it hasn't come from a single site however the architectural center of the PC part is in the Valley.

 

[Bjorn]

You'll never have "the same workload dispatched" as there will always be different core elements of the teams inolved, for instance I'll wager that most of the silicon layout and.....

Just out of curiosity, any idea on how Nvidia is working in this regard ?

 

[Dave Baumann]

AFAIK, the majority of the 3D designs come from the Valley while the plaform elements come from Texas.

 

[Sabastian]

You'll never have "the same workload dispatched" as there will always be different core elements of the teams inolved, for instance I'll wager that most of the silicon layout and.....

Just out of curiosity, any idea on how Nvidia is working in this regard ?

I have wondered about that before. nVidia design teams are all situated in Santa Clara AFAIK so in terms of their internal organization I think it would be less complex. nVidia are less transparent it seems and management doesn't seem to feel that their internal structure is worth making mention of.. unless they have and I missed the article all together. I have seen nVidia show off their state of the art labs and stuff but no mention of teams IIRC.

 

[Evildeus]

[action]shuffles crap out of the way on my desk[/action] WTF.. what do you call it when more then one organization works together on any project? A team effort... right? How else can they do that without coordinated work? If they are working in a coordinated manner then indeed they are unified.. That is the point. You can brood over that and be mystified about it for as long as you like but I am done talking about it.

Yeah, and if 90% of one site is not working with the other 2 they are not coordinated

 

[Evildeus]

You'll never have "the same workload dispatched" as there will always be different core elements of the teams inolved, for instance I'll wager that most of the silicon layout and implementation will come from the Valley, while all three sites will be working on the R&D that goes into the final silicon. Again, this is the case for R600 - all three sites have helped to develop it, in that technology that goes into it hasn't come from a single site however the architectural center of the PC part is in the Valley.

Of course, but the point of being unified, is to be able to dispatch workload efficiently where it can be. Before the R800 it doesn't seems possible, the Marlborough will be just some little input in this but can't be completly used.

Well, it seems we won't agree, so let stop here, you have made your mind, and mine won't change, because we have different conception of "unified and coordianted".

 

[PurplePigeon]

A few loosely connected thoughts related to the nVidia CC and the Orton interviews...

1) Given that nVidia stated that the target was 6xxx parts from top to bottom only by the end of the year, possibly one factor working against them is that SM 3.0 will not be widely available in the low-end for some time. Less incentive for game developers (possibly somewhat offset by higher spending in TWIMTBP to encourage use of SM 3.0 features?).

2) Manufacturability and yield were obviously big concerns for both companies. Speculation: there were rumours before of R420 just having VS 3.0, so any possiblity that there's a speck of truth to this and a refresh having VS 3.0 at the end of this year? It seems to me that ATI will only introduce new features when they feel that they can provide them with high performance and reasonable margin using the current fab processes available. Perhaps they will choose a gradual introduction of SM 3.0 after all?

3) The statement about the relative die size of nv40 and R420, ie. very close despite the large disparity in transistor count, is still very interesting to me... I realize that it has often been stated that the two companies count transistors differently, but bear with me. I am not well-versed in semiconductor manufacturing issues, but I am wondering if there would have been any benefit in less dense transistor placement with respect to attaining yield at a given high Mhz. ATI previously stated that they would be willing to sacrifice margin, if I recall correctly. Perhaps a larger die than strictly necesary results in higher cost, but the larger die gives a greater number of chips which can be clocked at the high end?

 

[BRiT]

Avialability of the PRO doesn't really suggest much in the way of yield issues, although thats not at the full spec - I've heard some things about yields of R420 that will negatively impact some of the X800 line, but thats likely to hit the SE edition most...

Is that to say that yields of the 16 and 12 pipeline parts are so high that the 8 pipeline only SEs are hard to come by?

 

[Evildeus]

Well there's only 2 possibilities, X800XT or X800 se, so pick your choice. DB seems to point out X800se...

 

[MrBond]

Avialability of the PRO doesn't really suggest much in the way of yield issues, although thats not at the full spec - I've heard some things about yields of R420 that will negatively impact some of the X800 line, but thats likely to hit the SE edition most...

Is that to say that yields of the 16 and 12 pipeline parts are so high that the 8 pipeline only SEs are hard to come by?

That's what it sounded like to me, and there's certainly precedent for that happening before. 9500 anybody?

Of course, the common thinking would be that the yields on the top two boards are low enough that there will be an excess for the SE boards.

 

[AlphaWolf]

Avialability of the PRO doesn't really suggest much in the way of yield issues, although thats not at the full spec - I've heard some things about yields of R420 that will negatively impact some of the X800 line, but thats likely to hit the SE edition most...

Is that to say that yields of the 16 and 12 pipeline parts are so high that the 8 pipeline only SEs are hard to come by?

Perhaps we won't see an 8 pipe SE at all then, but a 12 pipe SE?

12pipes ~400mhz core, with 400mhz ddr1.

 

[Gunhead]

(Everyone else notices that while both nV40U and R420PE are made on the same .13 micron manufacturing process there's a significant clock-rate disparity between them, . . .)

Um, as one of "everyone else", I beg to disagree.

First, I don't see the same .13 micron manufacturing process; I see two different .13 micron manufacturing processes. Different process specifications, different fabs (it's not like TSMC and IBM jovially share the internal know-how, so the production lines are bound to be somewhat different)...

Second, I see a considerable transistor count difference, which in my eyes goes a long way to explain the clockspeed difference. [And then it's another matter altogether whether Nvidia has made good use of those transistors. I gladly leave that discussion to others -- I'll be busy scraping up enough moola for a shiny new X800XT, myself.]

So there. Just for the record

I don't think Orton had factual grounds for any surprise on NV40's clockspeed, and I think he knew that too. Not that I was much bothered by his remarks. Par for the course in the business. And he's a genuinely likable guy. Even his FUD is kinda likable

 

[WaltC]

...
3) The statement about the relative die size of nv40 and R420, ie. very close despite the large disparity in transistor count, is still very interesting to me... I realize that it has often been stated that the two companies count transistors differently, but bear with me. I am not well-versed in semiconductor manufacturing issues, but I am wondering if there would have been any benefit in less dense transistor placement with respect to attaining yield at a given high Mhz. ATI previously stated that they would be willing to sacrifice margin, if I recall correctly. Perhaps a larger die than strictly necesary results in higher cost, but the larger die gives a greater number of chips which can be clocked at the high end?

I don't know what you mean by your last sentence, since generally the idea between yields and die size is the smaller the better. Don't forget low-K, however, which ATi is using and nVidia is not. The idea behind low-K is to clock higher, draw less power, and run cooler than you could achieve with the identical process, sans low-k.

 

[WaltC]

First, I don't see the same .13 micron manufacturing process; I see two different .13 micron manufacturing processes. Different process specifications, different fabs (it's not like TSMC and IBM jovially share the internal know-how, so the production lines are bound to be somewhat different)...

They are definitely two different processes, certainly. One big difference is one is low-k, the other is not. However, both products are advertised to be manufactured at the same .13 micron process size by their manufacturers, so we don't have a comparison like we did with R3x0 on .15 and nV3x on .13, which is the point I've laboriously tried to make. I guess we could get real picky and start looking at .13 micron cpus and chips and start second-guessing the manufacturer's specs and saying "Is this really .13 microns?" or "Is that really .09 microns?" but what's the point in doing so? The only point to be made here is that both are .13, one is low-k and the other isn't--and both chips are manufactured by way of the elective choices made by their respective manufacturers.

Second, I see a considerable transistor count difference, which in my eyes goes a long way to explain the clockspeed difference. [And then it's another matter altogether whether Nvidia has made good use of those transistors. I gladly leave that discussion to others -- I'll be busy scraping up enough moola for a shiny new X800XT, myself.]

What I see is nVidia counting every transistor in the die and reporting 222M, and ATi excluding cache and other transistors from their advertised count of 160M transistors, and I see die sizes which are closer in size than their respective transistor counts seem to indicate, so I suspect the actual difference there is much closer than it appears from the various specifications. Whether nVidia is over-reporting or ATi is under reporting, or both are doing some of each--I cannot say. I will say the nV40, based on die size, seems to have more transistors, certainly. But exactly how many more I really couldn't say.

I don't think Orton had factual grounds for any surprise on NV40's clockspeed, and I think he knew that too. Not that I was much bothered by his remarks. Par for the course in the business. And he's a genuinely likable guy. Even his FUD is kinda likable

Yes, I agree, and you also have to consider the tone and tenor of the question he was answering. I thought Orton gave the answer the interviewer deserved for the question he asked...

 

[DemoCoder]

As far as what's new - Bjorn, come on, now don't be so rigid/closedmined. Features are nice, but usable features are what count.

Depends on how you count usable features. NV3x was bashed over the head for 18 months for lack of HDR support. No games used it, and Valve is stating they won't use it in HL2 because it's too slow on R300. (I speculate they might use it in rare circumstances or cut scenes where it won't perform badly)

The status of 3Dc, FP blending/filtering, geometry instancing, SM3.0, et al, are to be determined in the future as to whether they are "usable". I mean, how many games are using boat loads of normal maps over the last 2 years and need hi-res ones? FarCry, HL2, and D3 are probably the first, and D3/HL2 ain't out yet.

The only real universally used features are AA and AF, and I think NV40's 4xAA and 16xAF are emminently usable and good enough in IQ. Sure, sometimes 6x can be switched on with R420 depending on game and resolution, and sometimes temporal AA will work as planned on some games. But you know, sometimes HDR and SM3.0 might be usable as well. We don't know yet.

Battle for Middle Earth, for example, will be the first game to do large scale geometry instancing. It will be the first good test to see if it has any big performance advantages.

 

[PurplePigeon]

...
3) The statement about the relative die size of nv40 and R420, ie. very close despite the large disparity in transistor count, is still very interesting to me... I realize that it has often been stated that the two companies count transistors differently, but bear with me. I am not well-versed in semiconductor manufacturing issues, but I am wondering if there would have been any benefit in less dense transistor placement with respect to attaining yield at a given high Mhz. ATI previously stated that they would be willing to sacrifice margin, if I recall correctly. Perhaps a larger die than strictly necesary results in higher cost, but the larger die gives a greater number of chips which can be clocked at the high end?

I don't know what you mean by your last sentence, since generally the idea between yields and die size is the smaller the better. Don't forget low-K, however, which ATi is using and nVidia is not. The idea behind low-K is to clock higher, draw less power, and run cooler than you could achieve with the identical process, sans low-k.

Yup, I have a general understanding that low-k is a factor which allows higher clocks and draw less power.

Basically I am thinking of the "success" of the fabrication process as two elements: number of usable chips (16 pipe or 12 pipe say); and if a chip is usable, how high can it be clocked.

My (extremely) non-expert thinking on this is that with a relatively lower transistor density, ie. larger die size than strictly necessary, might lead to lower yield. But maybe the more generous spacing would reduce the number of hot spots, or signal leakage, or whatever, so that those chips that are usable would be able to be clocked higher than they would if everything was packed in as tightly as possible.

Basically speculating that there is a tradeoff between yield and attaining high clocks and that ATI purposely designed with a mild preference for high clocks. Not necessarily saying that the yields are bad, just that they may have been willing to sacrifice it a bit for faster chips. It could be one explanation for the die size.

(Of course, I'm making amateur speculations. I readily admit that I know less about semiconductor fabrication than most on this board I'm sure.)

 

[3dcgi]

Anyway, the fact remains, the NV4X has a lot more transistors and is a SM3.0 chip so critisizing them for not reaching the same clockspeeds isn't really fair imo.

I'm a little late to the discussion, but since when has saying you're surprised been critisizm? I don't think he was critisizing Nvidia at all with that quote. If nothing else Dave Orton is biased by his knowledge of Ati's designs. It's natural to assume that Nvidia would be reaching similar clocks speeds to what Ati was reaching. It's also natural to assume that it won't have a slower clock than the previous generation chip. Both assumptions would have been wrong, hence the surprise.

 

[jimmyjames123]

So, first he calls the issue a bit of nonsense thats going around - this is nonsense that NVIDIA's reviewer guides tell us.

I think that the "nonsense" that he was talking about was the fact that people were spreading the rumor that the 6800 Ultra requires a 480 watt power supply.

He then tells us that the 6800 Ultra was designed with an optional Power socket (note the past tense - if it was designed in such a fashion why haven't we seen it yet; he didn't state that it will be designed in that fashion (seeing as the boards that have already gone out clearly weren't designed in such a fashion, suggesting that they are still to design them in such a fashion yet).

I think you are arguing semantics here, and maybe reading too much into the statement. What Jen Hsung seems to be saying is that the 6800 was/is designed for the hardcore gamer, who would be interested in overclocking the cards and pushing them to the max. To account for headroom above core clock frequency, they needed to add the second molex connector.

He further states that some reviewers had one Power socket plugged in and other didn't - although I've not followed up every review, I haven't seen a case where a reviewer tried it with successful operation; indeed it would go against their own reviewers guide and further testing on the "reviewers boards" we've seen suggests that normal operation can't be achieved (again, contradicting JHH's words as he states "What all of the reviewers with one power connector was able to reach the standard frequency we ship at for GeForce 6800 Ultra").

What have been your experiences running the 6800 Ultra with one molex connector so far? Have you followed up yet with other reviewers regarding what their experience has been?

He also states that one power cord can supply about 350W - I think this is a little much for one cord.

I'm not sure how much one power cord can supply, but the single molex/single slot 6800 GT seemed to have run just fine using PSU's that would be appropriate with a 9800XT/5950U (ie, 350 watt PSU's). FS was even able to overclock their 6800 GT to slightly beyond 6800U levels.

Interestingly he also states that everyone of their boards will ship at the same speed, despite the 450MHz Ultras - not Ultra Extreme's according to UK PR - going to certain select vendors

Isn't this again just arguing semantics? The 450Mhz boards sent to reviewers were not marketed as 6800 Ultras, but rather as 6800 Ultra Extremes. The 350Mhz boards were marketed as 6800 GT. This was shown clearly in the few reviews that included these cards.

I think it is fair to say that Jen Hsun was spinning some things in favor of NV, but that is not so different from what many other CEO's do with their own companies, including ATI.