Analyst: Intel's Larrabee chip needs reality check

[nAo]

If I understand Nao properly I think that some TMUs could aggregated into a bigger piece.
You could have for example every 4 cores along the bus a texture unit which aggregate 4TMUs and 128KB of cache splitted into 4 pools.
That what you think about Nao?

Not entirely, as the ratio Cores/TMUs might be greater than 1. For example I would not be surprised if LRB had for each 2 cores a single TMU + 64kb cache to serve them.

 

[Nano]

I agree. Still a lot of unanswered questions and no absolute direction for the GPU market yet.