AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

I am not sure if about the conclusion. Yes, it a big redesign but it also something like a mix between GP100 and GP102. I fear that those NCUs will not be able to show their power in DX11.
 
Can anyone explain better how the primitive shader is supposed to work (and interact with current APIs) ?
 
So is there any answer to the question of WHEN with respect to Vega rather than the obvious answers given about WHAT Vega is about. There were rumours that Vega had passed RRA (South Korea) certification, so when does this baby land?
 
Still there is no have sufficient detail to draw any meaningful conclusion on the "HBC" thingy. Anything from page table magic to real hardware caching is possible.

If one assumes it is purely hardware, for 16GB the tag storage needed would be ranging from >2GB (64B granularity) to ~32MB (4KB page granularity, 52-bit physical address, 12-bit state, more if 64B lines in the page can have their own state). It doesn't seem to be maintained on-chip.

How it would interoperate with cache coherency protocols in the host when being part of an APU is another interesting question — would they just skip this level of allegedly hardware caching for system coherent accesses?
 
Squilliam said:
So is there any answer to the question of WHEN with respect to Vega rather than the obvious answers given about WHAT Vega is about. There were rumours that Vega had passed RRA (South Korea) certification, so when does this baby land?
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1H/2017. Given the many similarities with the Polaris Launch (fresh chips, hot off the foundry, timing of PR etc.), it is not unreasonable to assume a similar timeframe for roll-out.
 
revan said:
https://www.techpowerup.com/reviews/AMD/Radeon_Vega_GPU_Architecture/2.html
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While TPU claims it's not the same as HBM, I hold my ground on saying HBC = HBM, AnandTech seems to agree
http://www.anandtech.com/show/11002/the-amd-vega-gpu-architecture-teaser/3
Meanwhile it’s very interesting to note that with Vega, AMD is calling their on-package HBM stacks “high-bandwidth cache” rather than “VRAM” or similar terms as was the case with Fiji products.
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pTmdfx said:
Still there is no have sufficient detail to draw any meaningful conclusion on the "HBC" thingy. Anything from page table magic to real hardware caching is possible.

If one assumes it is purely hardware, for 16GB the tag storage needed would be ranging from >2GB (64B granularity) to ~32MB (4KB page granularity, 52-bit physical address, 12-bit state, more if 64B lines in the page can have their own state). It doesn't seem to be maintained on-chip.

How it would interoperate with cache coherency protocols in the host when being part of an APU is another interesting question — would they just skip this level of allegedly hardware caching for system coherent accesses?
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It was a little bit expected, than if it will bring some response or confirmation, thoses ones will raise even more questions. ( and speculation ). ( and i dont speak about HBC/HBM, just for a whole )
 
From anandtech's article:

First and foremost, today’s detail release is a teaser, not a deep dive, or even a preview. AMD is only releasing a few details about Vega, and those are being kept at a high level.
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What a waste of time, really.


With that website showing a counter, I thought there would be a proper CES keynote showing specs or at least performance comparisons.

Exactly who enjoys this sort of crappy marketing moves? They're only working towards irrelevancy towards future announcements.
 
ToTTenTranz said:
From anandtech's article:



What a waste of time, really.


With that website showing a counter, I thought there would be a proper CES keynote showing specs or at least performance comparisons.

Exactly who enjoys this sort of crappy marketing moves? They're only working towards irrelevancy towards future announcements.
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AMD never announced or hinted an any conference, presentations, livestream. It was clearly labeled as an Architecture Preview and that's exactly what was delivered. no need to be disappointed.
 
ToTTenTranz said:
From anandtech's article:



What a waste of time, really.


With that website showing a counter, I thought there would be a proper CES keynote showing specs or at least performance comparisons.

Exactly who enjoys this sort of crappy marketing moves? They're only working towards irrelevancy towards future announcements.
Click to expand...

its your own failure to understand disappointment from your own judgement of expectations isnt reality.
 
Ike Turner said:
AMD never announced or hinted an any conference, presentations, livestream. It was clearly labeled as an Architecture Preview and that's exactly what was delivered. no need to be disappointed.
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I failed to confirm that there was a CES keynote, but let's be honest though: who the hell makes a pretty video of a kid walking around playing drumbs and then slaps a website with a counter, just to lift an NDA about high-level features to some websites?

They're overblowing the information being released.
I stand by what I said when I think no one really enjoys this sort of thing.
 
ToTTenTranz said:
I failed to confirm that there was a CES keynote, but let's be honest though: who the hell makes a pretty video of a kid walking around playing drumbs and then slaps a website with a counter, just to lift an NDA about high-level features to some websites?

They're overblowing the information being released.
I stand by what I said when I think no one really enjoys this sort of thing.
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Considering the countdown actually said "Countdown to Vega Architecture Preview", I don't see what's the fuss is about - they delivered what they promised.
 
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