AFAICT, the NCUs are very power efficient so if there's anything wrong with Vega it might be in the back-end (also thinking back at
@Ryan Smith 's post where he guesses the hot spot in Vega 10 might be in the ROPs).
The compute-specific products versus gaming seem to give a quarter to a third of their power budget to graphics and the more aggressive clocking.
If the ROPs aren't being exercised in a compute load, there's also a significant chunk of the CU texturing block, shader engine front ends, and additional CU activity related to those unexercised front ends.
One would think that if the L2 was serving the ROPs clients decently enough their power cost might have improved, given the alternative is to directly spill/fill over the DRAM bus. If not, perhaps there is some confounding factor at higher power/clock settings like fewer stalls, a difference in the L2's power contribution, or the ROPs not getting the same amount of physical optimization as the NCUs did.
I was referring to the very specific implementation in Zeppelin though.
How specific does it need to get?
SME and SEV were cited specifically over a year ago, as was the structuring of their methods and implementation in the dedicated Security Processor.
They actually gave some vague poly throughtput (using NGG Fast Path that is) data in whitepaper. Just no clear details. At all.
The nature of the draw stream binning rasterizer and primitive shaders got multiple marketing slides and various internal figures based on internal estimates, and then a whitepaper and various statements/interviews by AMD engineers and staff over the course of six months.
If the contention is that we are to infer from AMD's current retreat into silence as a positive, Nvidia flat-out said nothing at all about the roughly equivalent feature change with Maxwell, and didn't say much for some time after outside testing outed the change.
To a more limited extent, Nvidia held off discussing delta compression for at least one product iteration, as part of the announcement was retroactive.