Anarchist4000
Veteran
I was wondering the same thing and only thing I can think of is that Infinity also crossed for PCIe lanes with Epyc. Having more than 16 lanes would make sense for certain "server" parts that may link components via Infinity. Mostly related to SSG hosted controllers for NVMe or SAN. APU/x2 could be another possibility as could a larger PCIe slot. A 32 lane PCIe slot wouldn't be unreasonable with unified memory on server. Without serving as a means to connect chips, I'm at a loss for how it could be server optimized.Koduri stated that Vega's fabric is optimized for servers, but I'm not sure what would be limiting it other than perhaps some additional overhead for items like generally unused error correction or expanded addressing. In fact, I'm not sure what "server-optimized" really adds if all the fabric is doing is sitting between memory, GPU, and standard IO.
There's the flash controller and I think the IO for that, though its impact should be modest.