yeap i have the same feeling as i had with ryzen amd is sandbagging (more or less) the gaming perfomance
this
or they just thought to focus on gaming on the vega refresh
AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion
this
or they just thought to focus on gaming on the vega refresh
You mean not the board powers but TGP?
Here's something I googled:
„He [Chris Hook] also talked a bit about the power consumption, from a TGP (Total Graphics Power) point of view. Hook reveals the future Radeon RX Vega Nano will have a GPU plus memory power consumption of 150W. This climbs to 165W for the RX Vega 56 and 220W for the Radeon RX Vega 64.“
https://www.dvhardware.net/article66988.html
Here's something I googled:
„He [Chris Hook] also talked a bit about the power consumption, from a TGP (Total Graphics Power) point of view. Hook reveals the future Radeon RX Vega Nano will have a GPU plus memory power consumption of 150W. This climbs to 165W for the RX Vega 56 and 220W for the Radeon RX Vega 64.“
https://www.dvhardware.net/article66988.html
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Thanks, was quite sure I saw that 220W somewhere else than just the power efficiency slide
CaptainGinger
Newcomer
Gamers Nexus has a piece on the power numbers.
http://www.gamersnexus.net/news-pc/3004-rx-vega-64-and-vega-56-power-specs-price
http://www.gamersnexus.net/news-pc/3004-rx-vega-64-and-vega-56-power-specs-price
Thanks, I am able to read the graph ok
I meant the concept that the "Boost" clocks are lower than the actual running clocks makes zero sense to me.
D
Deleted member 13524
Guest
Chris Hook's interview. With gamers nexus I think. It's on YouTube.
Pay more per GB? Per "chip"? Paying more for what? :\
How is Hynix behind samsung on tech they helped develop?
Rasterizer
Newcomer
While I'm not especially familiar with how GPUs work on any sort of deep level, I've been following the Vega story for a couple of months now out of curiosity and I registered here mostly to ask a series of questions about Vega's memory bandwidth. According to this: 
Vega FE (and therefore presumably RX) seems to be not only memory bandwidth bottlenecked, but to be bottlenecked at a bandwidth well below that of the older Fiji. I don't understand why this is the case? In theory, the two stacks of HBM2 on Vega should be capable of 484 GB/s vs the 512 GB/s that Fiji was theoretically capable of with its 4 stacks of HBM1, yet the test results I've seen so far show way lower bandwidth for Vega than the ~30 GB/s difference in theoretical maximums would suggest.
Vega FE (and therefore presumably RX) seems to be not only memory bandwidth bottlenecked, but to be bottlenecked at a bandwidth well below that of the older Fiji. I don't understand why this is the case? In theory, the two stacks of HBM2 on Vega should be capable of 484 GB/s vs the 512 GB/s that Fiji was theoretically capable of with its 4 stacks of HBM1, yet the test results I've seen so far show way lower bandwidth for Vega than the ~30 GB/s difference in theoretical maximums would suggest.It would be interesting to know how much the manufacturing cost picture differs. HBM2's greater utility (reliability, capacity, fault recovery, channel modes, etc.) makes it applicable and desirable for many more customers.
8-hi would be the most notable cost-adder to manufacturing it, if that option is chosen. Other elements like utilizing a new node for higher-capacity layers and improvements to gaps/mistakes in the early version of HBM could have actually improved costs.
Then there's the question of being willing to pay much more compared to first-gen HBM, and it's not clear what that is in absolute terms. HBM seems to have far fewer takers.
Anarchist4000
Veteran
They may have used a different process with differentl thermal properties. Makes sense with the different voltages and stack sizes we've seen. HBM design only entails making layers and a controller that functions within certain specifications. How the DRAM cells are made and on which process is another concern entirely.
Resource contention, driver bugs, or thermal/performance issues all could do it. The small difference between theoretical bandwidth can be largely written off as a clock multiplier or design choice. My money would be on thermal issues decreasing effective bandwidth with more frequent refreshes as mentioned a while ago. Many of the initial FE reviews were forcing clocks high with little consideration for thermal limits. Limits that ultimately would have lessened performance, hence why the undervolting tests were faster and using less power at the same time. Some of the power saving features like AVFS and tuned profiles would have a similar effect. Then consider RX has essentially half the stack height.
Some idea of what was actually being compared would be nice. If they were straight up comparing a 4/8-Hi stack of HBM2 to HBM1 then yeah 2x+ the price is to be expected. Bigger chips, 4x/8x the capacity, FINFET process all would have pushed that figure up and not necessarily make it "more expensive".
Unfortunately, Anton messed up the source link - or is that his way of telling us there is no source but original content?
Last I saw, Samsung has been leading Hynix in DRAM process transitions, which on its own can have a major impact if HBM2 was not planned to be a mass product prior to the current node, and even then the relative density and sophistication of a given generation of DRAM node per manufacturer can vary.
The statement was that customers were willing to pay twice as much, although as long as Hynix isn't a charity it will mean the price will match. I think FinFET isn't a meaningful distinction between HBM and HBM2, or any recent DRAM. The DRAM processes have had FinFET control transistors implemented already.
Some reasons for HBM2's odd power behavior so far may be dependent on what node HBM2 is getting, and if there are more improvements or a proces change still possible if the lower-volume DRAM got something older to start with. The maturation and tweaking can have a notable difference, if Ryzen owners hunting Samsung's B-die DRAM are any indication.
Anarchist4000
Veteran
I only included FINFET in regards to typically higher cost of process design.
I'd be curious to know if they made different tiers of HBM2. If fabrication of 8-Hi stacks on an old process at low speeds was economically advantageous. There are certainly applications where capacity and form factor are more important than bandwidth. And yeah the B-die scramble would be a good example. Hopefully AMD doesn't mix manufacturers within a SKU if that is the case.
For me, what said ryan there is Sk Hynix is behind Samsung in term of ready to sell production. Samsung is alleady ready to sell mass production of HBM2. it is not a question of technology or process..
but more a question of the Samsung capacity to put on mass production and ready to sell to customers any semi conductor product way faster than any other company.
( they have a massive amount of FAB, R&D and a massive amount of money to throw at it compared to any other semiconductor company. ( it is not for nothing that Samsung lead the memory market since...1993 ? And is estimated to beat Intel this quarter in global semiconductor 1st place ( Q1 2017 they was only 4% behind them )
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It could be. As stated, Hynix was long-involved in HBM's development. HBM2's additions to HBM are incremental enough that HBM2 is a final revision of the same JEDEC standard covering features and a generally unchanged interface.
There could be tweaks to the die thinning and stack build. I did see cross-section of NVidia's stack, and it looks like the ratio of die thinning is higher for HBM2, since the 4-hi in that case has far more silicon above the thinned dies. That might mean 8-hi doesn't need to change the stack height or possibly that GP100 is a taller chip than average.
That aside, HBM has features like its TSVs, wide interface, ECC for HBM2, and other elements that significantly compromise the Gb per die and/or put power consumption at a premium. To compensate for all that, it would come down to the DRAM array capacity and power consumption--and that is process dependent.
One item of note is that Hynix has lagged Samsung in DRAM node transitions by 1-1.5 years recently, which seems suggestive in this case.
D
Deleted member 13524
Guest
This isn't an answer to the question at hand.
And the article doesn't answer that either, and leaving the question up in the air makes the article worth as much as a press release from SK Hynix bragging making a lot of money but without exactly saying why.
"Customers are willing to pay twice as much" is the message in AT's article. Twice as much regarding what?
Twice as much per-GB or twice as much per 4-Hi stack?
2x per-GB means SK Hynix will be getting 8x more money per stack (4x more memory per-stack, 2x more money per GB, 2x4=8).
Consequently, IHVs would need to spend over 4x more money for the same bandwidth (twice the bandwidth-per-stack from , 8x more money-per-stack, 8/2 = 4x more for same bandwidth)
- This is an insanely good deal for SK Hynix and insanely bad deal for IHVs.
2x per-4Hi stack means IHVs will spend the exact same amount of money for the same bandwidth, key difference they're getting twice the memory amount this time and they get to save on interposer area.
- This honestly sounds like a better deal for IHVs than for SK Hynix, which is why I think they would be willing to go up to 2.5x more money per-4Hi stack. For IHVs to spend the same amount of money to get 4x more memory at the same bandwidth and save on interposer area and most probably power savings from using less chips looks like too good to be true, hence their willingness to spend 2.5x more money on a 4-Hi stack.
They compare with standard DRAM, so i only see it as GB.. ( 2x more for x GB ) ... 8GB of DDR or 8GB of HBM is still 8GB.. ( but with different bandwith ).. if you need 2 stack of 4GB for get 8GB instead of 4 DDR chips.. The article is not really clear anyway. ( or Hynix was not )
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Without knowing the exact context of the conference call, it very well could have been a characterization of revenue expectations to analysts or investors. In which case, saying they can extract twice as much money than they could with HBM makes sense.
I'm curious who is still paying for HBM and how much, or if this is a historical reference to whatever the theoretical price would have been for the specific KGSD used by AMD.