You're required frame buffer size is too small as it needs to hold color and depth buffers.2560*1600*4bytes/pixel~16MB, that's way too much. Does xenos renders to it's edram in tiles or does it operate at a lower resolution?
Perhaps 2 or 3 shrinks later.
AMD RV770 refresh -> RV790
- Thread starter w0mbat
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Originally read RV870 was one of their first chips, but think this has been pushed back to Q4. Heard absolutely no info at all about a low end RV720, I guess for AMD this might be more important as they dont sell a intel IGP.
Yes that's how they've been GPUs margins were in the low 40s and IGPs in the mid 30s so GPUs always won. Currently though the choice is between selling an IGP and the deep blue sea. If nvidia could get a dx11 igp out in time for windows 7 would think it would sell tremendously well. A lot of oems remember the 915/vista and would not like to repeat that.
Can not think offhand of any chip that has swapped transistor type on the same node. Original rumor of the chip was that it was the first chip on TSMCs new 55GT node, afterwards sometime later a few people said the RV670 was on 55GT but i think perhaps they were mistaken. Will need to search back through old processes see if i can find something.
Sorry - have been trying to source where i saw the 290mm2 claim last year and cannot find it. I might be misremembering
Definitely was larger than current RV770, alot of people throwing round a 270mm2 figure(& 960SPs) though no definitive source.Others are floating round 12 cluster(960SPs) at 700-750Mhz for Pro and 850-950Mhz for the XT. Am seriously thinking the performance is right, but the power consumption and price of this part is wrong. There are just not enough customers at the high price range, would work a lot better at US$250. Last generation about the only thing nvidia could get stick to the 4850 was the inadequate cooling/high temperatures, this part potentially looks to be a bit worse on that front.
Are you sure RV740 is at A11? That would be first revision on a new chip on a new process that has been delayed 6 months from its original launch date.
I read the original A11 740 worked but its power usage was really poor(ie oct/nov last year), so they were going back to try again. Seems a bit strange they would just sit on the original design till TSMC was ready without at least trying a respin to fine tune it while they waited.
Would imply all the delays have been TSMCs fault.
No rjc I'm pretty sure he was referring to A11 running at 700Mhz, not A11 being current. I think it's been to A13, might go for another waxing up before showing in retail.
ATI seems to want both low(er) power consumption (presumably no PCIe anymore) and high performance. Given that this card is perfectly suited for back-to-school seasons (at least the desktop part), the delays don't hurt that much.
I've also heard some shuffling on Chiphell that the RV740XT actually pars a 512MB 8800GTS (G92 full), which is extremely impressive for a ~100mm^2 chip... if true.
ATI seems to want both low(er) power consumption (presumably no PCIe anymore) and high performance. Given that this card is perfectly suited for back-to-school seasons (at least the desktop part), the delays don't hurt that much.
I've also heard some shuffling on Chiphell that the RV740XT actually pars a 512MB 8800GTS (G92 full), which is extremely impressive for a ~100mm^2 chip... if true.
There's this weird belief around here that a metal spin will fix clock speeds or power consumptions. That's really quite rare. After all, what exactly can you do by changing metal? To improve speeds, you could reroute a few wires to fix a crosstalk induced timing path. Or you could insert a spare buffer here or there along the way, if you're really lucky. (Both would fix your own mistake, not some kind of error of the fab, BTW.) And how to reduce power with a metal spin? Maybe there are some obscure way to do it? Feel free to suggest something because nothing specific comes to mind.
Metal spins are great to fix functional bugs, but their potential to fix speed or power problems are the exception rather than the norm.
Cookie Monster
Newcomer
Could it be lowering the core voltage i.e lowering the overall power consumption? I always thought that some of the main reasons of re-spins were to reduce power consumption/improve clock speeds (fixing bugs as well). Now since you mention this, can anyone clarify further on this?
Isnt this the case with GT206/GT200B and its 3 re-spins hence the B3 revision?
Yes, that's what I know as well. You decrease voltage and the power consumtion goes down. However, this cannot help agains leakage, which is becoming more and more of a problem with newer processes.
silent_guy was probably saying that between different chip revisions there isn't any methodology to fix power consumption as the core voltage cannot be, quite obvoiusly, lowered. The only way i can think of is still a "functional" fix - enabling/fixing (some of ) the chip's power saving modes.
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http://www.mfgquote.com/profiles/CenturyMetalSpinningCo-3527.htmlUmm, what are metal spins?
55*55 = 3025Hmm, TSMC's documentation indicates that scaling from 55->45/40nm should be ~0.55x, so on that basis you'd be right. I was under the impression it was more like ~0.67xCan't find the posting that led me astray...
Jawed
40*40 = 1600
1600/3025 = 0.53 ~ 53%
Jawed
Legend
This document:
http://www.tsmc.com/download/english/a05_literature/2_Advanced_Technology_Overview_Brochure_2007.pdf
says that 55nm is 90% of 65nm and that "45nm" is 50% of 65nm - which is how I got 55% for 55->45nm. Still can't find the post I was thinking of.
Jawed
http://www.tsmc.com/download/english/a05_literature/2_Advanced_Technology_Overview_Brochure_2007.pdf
says that 55nm is 90% of 65nm and that "45nm" is 50% of 65nm - which is how I got 55% for 55->45nm. Still can't find the post I was thinking of.
Jawed
A metal spin is a chip revision where only metal layers of a chip are changed and the base layer stays constant. Basically, you don't add any new transistors on the die, you just reconnect a few of them differently. To make this possible, a new chip has always a whole bunch of so called spare gates: unused logic elements that are sprinkled all across the chip that can be used when new logic elements are required for bug fixing.Umm, what are metal spins?
Most chips require metal spins before going in production (RV770 is a notable exception). Base spins are rare.
Since metal spins don't materially change the silicon (transistors stay the same), they usually don't result in significant changes wrt speed and power. (Except for crosstalk fixes.)
Metal spins are usually indicated by an increment in the minor version number.
E.g. going from A11 to A12 indicates a metal spin. Going from A11 to A21 could suggest a base spin. Going from Axx to Bxx could indicate going to a different process or a different fab. But each company has its own conventions.
If you want to lower the core voltage, all you have to do is lower the core voltage.
That is: you tune the external power supply. No need to change anything on the silicon.For metal spins, the prime objective is almost always bug fixing. There is very little you can do once you've nailed down your design and selected the process.
You can ask the fab to tweak process parameters a little bit to shift the silicon into a certain direction, but that also increases the chance that the characteristics of the resulting silicon will fall outside the desired range (and thus impact yield.)
It depends on the company conventions. Does the B in B3 mean that there were two base spins of the 55nm version or does the B in B3 mean it's the 55nm version with A being the 65nm version?
It's obvious that a 55nm version will have different speed and power characteristics, but that's generally not called a spin. The proper name is a shrink. A spin generally has a negative connotation because it means that bugs had to be fixed. A shrink is usually a cost optimization (that may require spins to get it right.) For those cases where a shrink is 100% logically equivalent to its original design, the prime reason to spin a shrink is to fix analog problems (ESD, IO pads, PLLs not behaving like they should.)
You're throwing a bunch of concepts together. Not that's there anything fundamentally incorrect, but it comes out confused.
The same piece of silicon will drastically leak less if you lower the voltage. Most of the leakage is ~ K * exp(Vgs-Vth), with Vgs the supply voltage. K is going up dramatically for some smaller high-speed process, but that's not really relevant in this discussion.
A number of techniques can reduce leakage for a given process (e.g. by using transistors with a different Vth depending on the required speed), but that's all base layer stuff. A metal spin won't help you there.
There are many ways to reduce the power consumption of a chip, but pretty much all of them deal with reducing the consumption when the chip isn't operating at 100% performance level. Very little can be done to do something about the latter, other than making changes at the architecture/design level.
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with nV they used A for the 65nm GT200 and G92 and B for the 55nm (hence the popular G92b codename for the 9800GTX+) and it either becomes G92c when it hits 40nm or something like gt216/8 in it's eternal slide down from G80.
Fixing signal integrity issues can potentially lead to some power savings, since a favorite way to defer running into them is to nudge voltage levels higher.
For more significant changes, we have a historical example in AMD's Thoroughbred A and B cores.
Fixing the poor clocking and heat issues took a change in layout and at least one addtional metal layer, something more than just a respin.
For more significant changes, we have a historical example in AMD's Thoroughbred A and B cores.
Fixing the poor clocking and heat issues took a change in layout and at least one addtional metal layer, something more than just a respin.
Ok sorry should not have written the sentence that way. How about:
Back around oct(might have been earlier cant remember exact dates) A11 740 chip was functional but the power consumption was disappointing. They decided to to respin to fix unknown problems, this i think did not work out as well as hoped (reports of problems around early jan). Not sure what course of action they have since pursued except that there are rumors of release around may.
Questions i can see is:
[STRIKE]Are they going with original A11 for some reason?[/STRIKE] (No need to worry, thanks Tchock!)
Original design was for a chip without a power connector, looks like will need one now, whose fault is that?
Alternatively, given the late april/may release rumor is true, are they now waiting for results of another spin or is it all up to tsmc?
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RV770 required a spin. It was RV670 that did not. And you never want to be the designer that causes a new base tapeout. :smile:
I agree with silent_guy that metal spins are primarily for bug fixes. I've seen timing fixes with a metal spin, but as silent_guy said that is the exception rather than the rule.
It shouldn't be necessary if the software predictions match the results of real hardware. And there's usually not a lot you can do in a metal spin other than add buffers to a path and use gates with a higher drive strength.
GTS240 is an overclocked 9800GT
I guess the RV740 came in slightly higher than Nvidia's expectations ..
I guess the RV740 came in slightly higher than Nvidia's expectations ..
If the 240 is as cheap as its name would suggest, that sounds like a pretty sweet card. It should be as fast or faster than an 8800GTX for the most part.