AMD RV770 refresh -> RV790

Prelim info might be scary wrong too.
AMD keeps their presentation slides very close till launch.



20% is a hard figure to justify from either a clock raise (too much) perspective or a chip redo perspective (too little)...
 
This confusion is as thorough as RV770's :p

RV740 is 40nm and should be the first 40nm chip. One rumour said RV740 was supposed to have been a November/December/January (take your pick) launch which was pushed back by TSMC and that the implication is that RV790 is also 40nm because it would have fitted in nicely as a February/March/April launch, after RV740.

That does make a fair amount of sense, since I'm expecting RV740 to perform like HD4850 but with a 128-bit bus, GDDR5 and a real puzzler of a question over its RBE count/configuration. RV740 would be a little monster.

That would lead into RV790 also being a monster, and the only way to not choke it is to give it more RBEs or up the Zs per RBE. In which case GTX285 would be dust.

Trouble is, I think RV790 is just a boring, timid, refresh on 55nm.

Jawed
 
205mm² on 55nm would be pretty damn incredible - I don't quite buy it yet. Unless it's a 192-bit GDDR5 GPU with no GDDR3 support maybe?
 
Maybe they threw out the CFX-port, added two or one additional cluster and did some floor plan optimization to end up at 205mm^2 at 55nm.

Back in October, there were some rumors about a 205mm² 1.5TFLOPs(what would be RV790s ~850MHz @880-960SPs) GPU:
http://translate.google.ch/translat...rv870-neue-details&sl=de&tl=en&hl=de&ie=UTF-8

Taping out an entire new chip on the same process, with ~10% improvement in clocks and alu's, sound mighty unlikely to me. :rolleyes:

Instead, doing the same effort for a smaller node seems more plausible to me.
 
2 extra clusters would add about 20mm2 to the die. So that's a starting point of 276mm2.

Deleting CrossFireX Sideport seems extremely unlikely to save 70mm2 - that's an area equivalent to ~7 clusters!

Jawed
 
Is that really just so easy? No extra wiring, no extra space taken up by the scheduler, no increased complexity in data paths to and fro?
 
Is that really just so easy? No extra wiring, no extra space taken up by the scheduler, no increased complexity in data paths to and fro?
That's just a reckless guess, ignoring routing. As to scheduling, I still haven't worked out how this is configured across the die - i.e. how much scheduling is within a cluster and how much is outside...

Jawe
 
Well, TBH, the specu posted earlier makes me think Jawed may be along the right track. If they have the samples and are telling the world about the clocks, why wouldn't they say that it has x more alu's if it had? But then why haven't they said that it has same either. Of the two, I find the earlier more probable, though I can't figure out why rv790 would be on 55nm.

And since tsmc's 40 nm process leaks madly, it would seem reasonable that a 40 nm chip won't have more clocks. After all, IIRC rv670 and rv770 have the same clocks too, to keep the power in check.
 
For what it's worth, the rumours are for more than one 40nm chip. Has "RV720", RV710's replacement, ever been mentioned? If not, then doesn't that make RV790 likely to be the other chip an 40nm?

205mm2, say 16 clusters, 1280 ALU lanes, ~2.2 TFLOPs with a 256-bit bus and no change to the RBEs.

Jawed
 
For what it's worth, the rumours are for more than one 40nm chip. Has "RV720", RV710's replacement, ever been mentioned? If not, then doesn't that make RV790 likely to be the other chip an 40nm?
The 3 leadoff 40nm chips are - RV740, GT216 and GT218. Not sure what else comes after, amd also needs something to replace their igp, also i swear i read last week somewhere jsen huang let it slip ion would dx11 before the end of the year(will spend rest of today looking for this link ;)).

205mm2, say 16 clusters, 1280 ALU lanes, ~2.2 TFLOPs with a 256-bit bus and no change to the RBEs.
The rumor i heard was ~290mm2, that was last year. Wasn't sure if the extra size was due to the change from 55GP to GT or they had added extra units. Sorry is not 40nm, the vr-zone link said 1.3V above TSMC's 1.2V max for 40nm...exceeded on the first chip, doesnt seem very probable.

Is interesting planning to try and put out a US$300 part, that seems way high without a lower priced volume part. Maybe they did something to the MC/RBE's so it only rally works well with GDDR5, samsung expects GDDR5 to be 20% of the market this year.
 
i swear i read last week somewhere jsen huang let it slip ion would dx11 before the end of the year(will spend rest of today looking for this link ;)).

This? http://blog.laptopmag.com/nvidia-ceo-sounds-off-on-netbooks-ion-platform-tegra-and-mids

JHH said:
I don’t really know if they are or not. They haven’t told me. Our focus is to build the most amazing products that the world has seen, and hopefully surprise the industry with what we can achieve. We’ve always believed that the GPU is becoming more important. With Ion, we’ve brought Cuda, Open CL, and DirectX 11 all the way down to the most cost-effective platforms in the world. This is a really good platform for consumers. Customers and consumers are well served by having this platform.

Could be a simple slip of the mind. He would obviously have DX11 on the brain these days.
 
For what it's worth, the rumours are for more than one 40nm chip. Has "RV720", RV710's replacement, ever been mentioned? If not, then doesn't that make RV790 likely to be the other chip an 40nm?

205mm2, say 16 clusters, 1280 ALU lanes, ~2.2 TFLOPs with a 256-bit bus and no change to the RBEs.

Jawed

alu count seems reasonable, but memory bandwidth seems to have very little growth compared to rv770, when it was already texturing limited in certain games.

This makes me wonder, could amd decide to implement some edram (ie xenos like) stuff on future stuff (may be not rv790/740 but on rv8xx perhaps or may be even later), that would relieve a lot of bandwidth requirements. It could be on die if necessary and since display resolutions don't grow as fast as moore' law, the cost could be manageable/negligible in not too distant future.
 
alu count seems reasonable, but memory bandwidth seems to have very little growth compared to rv770, when it was already texturing limited in certain games.

This makes me wonder, could amd decide to implement some edram (ie xenos like) stuff on future stuff (may be not rv790/740 but on rv8xx perhaps or may be even later), that would relieve a lot of bandwidth requirements. It could be on die if necessary and since display resolutions don't grow as fast as moore' law, the cost could be manageable/negligible in not too distant future.

Even though the resolutions don't grow rapidly anymore, 2560x1600 requires already damn lot of it, can't see it as really reasonable solution anymore, unless they go for "real tiler" (which to my understanding would cut the mem requirements for edram)
 
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