I do not think that would matter, since the bus traffic is not what is being compressed. Compression is about accesses saved, not how the accesses travel over the bus. A normal GDDR5 transaction has a burst length of 8 and is going to provide 32 bytes, which may satisfy a physical ROP cache line since we don't know its granularity, but we know it would require two to satisfy a vector cache request.I don't think frame buffer compression is as effective on HBM than GDDR5 since there are only 2 burst lengths rather than (IIRC) 4 for GDDR5.
A 128-bit HBM burst with burst length 2 is going to provide 32 bytes.
The article's calculation is a straightforward 4096*2*1050/300W. The memory bus doesn't get to draw power or dissipate from a budget not on the card.No. HBM improves perf/W significantly for the memory interface, but the memory interface is only a small fraction of overall GPU power. The shader array is dominant, and its perf/w is unrelated to the memory interface.