AMD: Navi Speculation, Rumours and Discussion [2019-2020]

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Except for the fact that the apu will be soc and no cpu + io/gpu
What is the source of the info? I'd say there is a 16 CU Navi die (with 12 CU cut-down version) and 10 CU Navi die (with 9 CU cut-down version). Combination of 14nm IO + 7nm Zen 2-chiplet + two different 7nm Navi-chiplets would allow immense flexibility. I'm sure the semi-custom division would love it. Btw. the 16 CU die could be also sold separately as dicrete low-end.
 
Except for the fact that the apu will be soc and no cpu + io/gpu
One has to make a distinction between the rumors and the speculation. He clearly said he doesn't have information about how the dies are configured, and he said he's speculating about the APU using the same chiplets.
 
Probably a combination of 15-20% higher clocks and a 20-30% improvement in efficiency for the new architecture?

Didn't realize that RTX 2070 is faster than Vega64 in most real-world applications. If a new mid-range part really outdoes current enthusiast-level part, might explain why they say Navi looks 'exceptionally good'.
15-20% higher clocks than what? Vega 10? Vega 20?
 
What is the source of the info?
Anandtech asked AMD whether their next Zen2 based APU would be chiplet design or not. AMD replied it would not. So this means the 2020 7nm Zen2-based Renoir APU will not employ the chiplet + IO composition. It makes sense - margins would be tight laptop APUs.

https://www.anandtech.com/show/1385...nt-on-matisse-cpu-tdp-range-same-as-ryzen2000 Let's hope this won't be another garbage info coming from Anand's...

Probably a combination of 15-20% higher clocks and a 20-30% improvement in efficiency for the new architecture?
A GCN-based chip achieving 2GHz, 1.3 IPC of Vega with a sensible TDP sounds highly unlikely.
 
According to netkas.org, the Navi strings do not represent different chips or products.
Navi10, Navi16, Navi9 is not chip names, the number is just c++ name separator
Function names as is:

$nm AMDRadeonX6000HWServices | grep Navi

__GLOBAL__sub_I_AMDRadeonHWServicesNavi.cpp

__ZN38AMDRadeonX6000_AMDRadeonHWServicesNavi10MatchTableE

__ZN38AMDRadeonX6000_AMDRadeonHWServicesNavi10gMetaClassE


[…]

with c++ name demangling: $ nm AMDRadeonX6000HWServices | grep Navi | c++filt

__GLOBAL__sub_I_AMDRadeonHWServicesNavi.cpp

AMDRadeonX6000_AMDRadeonHWServicesNavi::MatchTable

AMDRadeonX6000_AMDRadeonHWServicesNavi::gMetaClass


[…]


Navi 16, Navi 12, Navi 10, Navi 9

they are not codenames, so max 1024SP for NAVI16
There were strings in late 2016 containing "Polaris10," "Polaris12," "Polaris10XT2," and "Vega10," which apparently refer to codenames. That was a different file though.
 
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30/40% faster was surely above their expectations.
Not sure what that 30%/40% refers to, but AMD is probably happy about how Turing turned out, because if you exclude the new features, its perf/area (or perf/transistor) is quite bad compared to Pascal (30% worse or so) (although it still does well against Vega, and at least perf/w didn't get worse). That'll give AMD some opportunity to catch up with Navi in theory, albeit for now I remain sceptical...
 
Interesting to note, that when Vega (code name for chip) was released Dr Su said that the name was so "cool", that they would keep the "chip" name for marketing. Hence Radeon Vega X.

The Card AMD announced at CES is a Radeon VII (Seven), no mention of Vega. Even though I have heard Dr Su herself, mention the Radeon Seven as Vega2 several times...

Radeon VII was actually suppose to be Radeon Vega 2... (ie: Navi).
 
This is interesting. The upcoming desktop APUs - Raven2, Picasso and even Renoir are GFX9.0* based. The Navi architecture was reported only for that recent supposedly console based APU - Gonzalo.
Renoir GFX9? Is there actual source for this? Only roadmap I've seen mentioning Renoir doesn't say anything about which architecture it would use for absolutely anything
 
Anandtech asked AMD whether their next Zen2 based APU would be chiplet design or not. AMD replied it would not. So this means the 2020 7nm Zen2-based Renoir APU will not employ the chiplet + IO composition. It makes sense - margins would be tight laptop APUs.

https://www.anandtech.com/show/1385...nt-on-matisse-cpu-tdp-range-same-as-ryzen2000 Let's hope this won't be another garbage info coming from Anand's...
Devil is in the details, they didn't actually say it won't be chiplet design, they said it wouldn't use Matisse design
 
Seeing the size of the I/O dies, even considering, they have a higher percentage of analogous circuirty and are in an older process tech, I wonder if they don't have enough space in them to at least provide „functional“ Vega GFX. Maybe nothing like 16 CUs or the like, but 4 to 8. OTOH, if that was the case, I cannot think of any sane reason for AMD not to announce APU parts at the same time, except maybe inventory.
 
Navi being officially GCN
Well there were conflicting reports abot Navi being the last GCN or first post-GCN architecture... I just meant better efficiency overall, whether from IPC and scheduling, caches and data compression, or automatic primitive shaders, geometry binning and other features which couldn't work in Vega for some undisclosed reasons.

RTX2070 only has 1/2 TFLOPS of Vega 64 yet it's 10% faster in real world applications... can't attribute it all to the voodoo magical tensor cores.
 
Well there were conflicting reports abot Navi being the last GCN or first post-GCN architecture... I just meant better efficiency overall, whether from IPC and scheduling, caches and data compression, or automatic primitive shaders, geometry binning and other features which couldn't work in Vega for some undisclosed reasons.

RTX2070 only has 1/2 TFLOPS of Vega 64 yet it's 10% faster in real world applications... can't attribute it all to the voodoo magical tensor cores.

Maybe tmu/rops too ? 64 is not a limited thing for Vega ?
 
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Radeon VII and GeForce RTX 2080 have almost the same transistor budget and Radeon VII is expected to perform just a bit worse than GeForce RTX 2080. That doesn't indicate any architectural problem at all. The only problem is lower energy efficiency. Performace per transisor at the same clock is very close.
 
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