AMD: Navi Speculation, Rumours and Discussion [2019-2020]

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SimBy said:
Whats the latest on N21 and bus width? Everyone still on the 256bit train? As a contrarian I have to call BS.
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I think we are at the point in the cycle that its 16 gigs of HBM2 with a 128megs of on die cache to and also 16 gigs of gddr @ 256bit bus width. AMD just wants all the bandwidth.


But in all honesty some think the high end is a 128 megs of cache with HBM2 and the lower edition is 128 megs of cache with gddr @ 256 bit bus

Moores law is bringing up mark cerny saying that amd redesigned the chip to keep data where its needed as speculation that it has that cache and cache scrubbers. Cerny says if you see a card with our influence on it at the same time then we did our job.

Moores law says there is a navi 21 sample 60cus at 2ghz , 256bit 16gb gddr 6 , likely has a large set of cache and it isn't the full die

I gotta say however as a tech geek all this is so much fun. Nvidia announcement into xbox stuff into a day of oculus , sony , geforce benchmarks , new garmin watch , new apple watch.... seriously man today is nuts
 
eastmen said:
I think we are at the point in the cycle that its 16 gigs of HBM2 with a 128megs of on die cache to and also 16 gigs of gddr @ 256bit bus width. AMD just wants all the bandwidth.


But in all honesty some think the high end is a 128 megs of cache with HBM2 and the lower edition is 128 megs of cache with gddr @ 256 bit bus

Moores law is bringing up mark cerny saying that amd redesigned the chip to keep data where its needed as speculation that it has that cache and cache scrubbers. Cerny says if you see a card with our influence on it at the same time then we did our job.

Moores law says there is a navi 21 sample 60cus at 2ghz , 256bit 16gb gddr 6 , likely has a large set of cache and it isn't the full die

I gotta say however as a tech geek all this is so much fun. Nvidia announcement into xbox stuff into a day of oculus , sony , geforce benchmarks , new garmin watch , new apple watch.... seriously man today is nuts
Click to expand...

That part of Cernys talk was interesting and implies it was actually their idea. Still, PS5 has 36 CUs. A much smaller beast to feed.
 
SimBy said:
That part of Cernys talk was interesting and implies it was actually their idea. Still, PS5 has 36 CUs. A much smaller beast to feed.
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My guess is that both sony and MS are running navi 2 and that AMD already had these being developed based on their own needs.

I'd also imagine that a 36 cu part will have less cache than 128megs. They could put less cache and save die space.
 
Regarding the memory bandwidth and bus size if we look at Nvidia with Ampere they are using the same 14Gbps x 256bit on GA104 as they used on TU106, which on paper at the moment looks like something around the 1.5x end performance difference mark. With the white paper out on that there also doesn't seem to be significant, at least nothing they are overtly revealing compared to the past, that they've done to increase effective bandwidth.

With that in mind the idea of 16 Gbps x 256 bit, especially if you do add something like the the rumored cache, on a 80CU (2x Navi 10) is not really outlandish so speak. If we just use linear scaling at 16/14 x 1.5 it would mean that should scale to something 1.71x faster at the same rate without any other advantages. Note that this doesn't mean Big Navi would be capped at around 1.71x faster.
 
SimBy said:
That part of Cernys talk was interesting and implies it was actually their idea. Still, PS5 has 36 CUs. A much smaller beast to feed.
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CPU still wants its bite of the pie.

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The HBM cards:

https://www.anandtech.com/show/9621/the-amd-radeon-r9-nano-review/2
[URL]https://www.anandtech.com/show/9421/the-amd-radeon-r9-fury-review-feat-sapphire-asus/2[/URL]
https://www.techpowerup.com/gpu-specs/radeon-vii.c3358#gallery-7
https://www.techpowerup.com/gpu-specs/radeon-rx-vega-64.c2871#gallery-4

all place the GPU package "close" to the PCI Express slot interface, lower down the board. None of the leaked images of supposed Navi cards have a low position for the GPU package, therefore they are not HBM. They are all trying to fit GDDR modules between the GPU and the PCI Express slot interface.
 
New AMD Patent Application to reduce traffic from individual CUs to L2/memory by checking the data from other CUs first, resulting in many CUs configured in a crossbar.

20200293445 ADAPTIVE CACHE RECONFIGURATION VIA CLUSTERING
Abstract
A method of dynamic cache configuration includes determining, for a first clustering configuration, whether a current cache miss rate exceeds a miss rate threshold. The first clustering configuration includes a plurality of graphics processing unit (GPU) compute units clustered into a first plurality of compute unit clusters. The method further includes clustering, based on the current cache miss rate exceeding the miss rate threshold, the plurality of GPU compute units into a second clustering configuration having a second plurality of compute unit clusters fewer than the first plurality of compute unit clusters.
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(One of the inventors mentioned is AMD fellow Gabriel Loh)
upload_2020-9-17_13-33-28.png
 
Jawed said:
CPU still wants its bite of the pie.

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The HBM cards:

https://www.anandtech.com/show/9621/the-amd-radeon-r9-nano-review/2
https://www.anandtech.com/show/9421/the-amd-radeon-r9-fury-review-feat-sapphire-asus/2
https://www.techpowerup.com/gpu-specs/radeon-vii.c3358#gallery-7
https://www.techpowerup.com/gpu-specs/radeon-rx-vega-64.c2871#gallery-4

all place the GPU package "close" to the PCI Express slot interface, lower down the board. None of the leaked images of supposed Navi cards have a low position for the GPU package, therefore they are not HBM. They are all trying to fit GDDR modules between the GPU and the PCI Express slot interface.
Click to expand...

It's the trend, and you're probably right, but its not strictly necessary. The Radeon Pro Vega II Duo for Apple moved the chip further up the PCB (admittedly it was a pretty packed PCB).
https://www.guru3d.com/news-story/announcing-the-new-amd-radeon-pro-vega-ii-duo.html
 
eastmen said:
I think we are at the point in the cycle that its 16 gigs of HBM2 with a 128megs of on die cache to and also 16 gigs of gddr @ 256bit bus width. AMD just wants all the bandwidth.


But in all honesty some think the high end is a 128 megs of cache with HBM2 and the lower edition is 128 megs of cache with gddr @ 256 bit bus

Moores law is bringing up mark cerny saying that amd redesigned the chip to keep data where its needed as speculation that it has that cache and cache scrubbers. Cerny says if you see a card with our influence on it at the same time then we did our job.

Moores law says there is a navi 21 sample 60cus at 2ghz , 256bit 16gb gddr 6 , likely has a large set of cache and it isn't the full die

I gotta say however as a tech geek all this is so much fun. Nvidia announcement into xbox stuff into a day of oculus , sony , geforce benchmarks , new garmin watch , new apple watch.... seriously man today is nuts
Click to expand...
Cerny said quite the contrary, that sometimes some things like cache scrubbers are very specific for their chip and dont go into AMDs products.
 
Jawed said:
CPU still wants its bite of the pie.

all place the GPU package "close" to the PCI Express slot interface, lower down the board. None of the leaked images of supposed Navi cards have a low position for the GPU package, therefore they are not HBM. They are all trying to fit GDDR modules between the GPU and the PCI Express slot interface.
Click to expand...

upload_2020-9-18_0-23-43.png

How does it look?
 
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ethernity said:
New AMD Patent Application to reduce traffic from individual CUs to L2/memory by checking the data from other CUs first, resulting in many CUs configured in a crossbar.

20200293445 ADAPTIVE CACHE RECONFIGURATION VIA CLUSTERING

(One of the inventors mentioned is AMD fellow Gabriel Loh)
View attachment 4637
Click to expand...
It describes a mechanism allowing CU-private caches to collectively operate as if they are one multi-banked cache when necessary (high capacity = more sharing = higher hitrate). It sounds like a researched alternative scheme to the always-shared GL1 cache introduced by RDNA, and maybe it is destined for CDNA.
 
ethernity said:
View attachment 4643

How does it look?
Click to expand...
The "doors" on the backplate have to be for something. They keep bugging me. Someone else said the bigger door looks like it could fit m.2 drives underneath but I don't know if that would even be worthwhile for gaming. I know AMD has already made cards with m.2 drives but with DirectStorage becoming a thing, I feel like there are more elegant solutions like what nVidia did.
 
t0mb3rt said:
The "doors" on the backplate have to be for something. They keep bugging me. Someone else said the bigger door looks like it could fit m.2 drives underneath but I don't know if that would even be worthwhile for gaming. I know AMD has already made cards with m.2 drives but with DirectStorage becoming a thing, I feel like there are more elegant solutions like what nVidia did.
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Doors?!
 
SimBy said:
Doors?!
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bolt-on-cadillac-lambo-doors-vertical-doors-lsd-door-kit.gif
 
Wasn't there talk some years ago, something Wang said, about one day having something like DX12 run within the GPU... or they are almost to that point, etc.. ?
 
t0mb3rt said:
I mean those 2 screws on the back sure look like they're holding on some removable plates. There's even places to fit your fingernail underneath milled into the metal.
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I'm pretty sure there's nothing interesting under the backplate. At least according to the ES board we've seen.
 
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