You mean the PS5 presentation where they compare RDNA2 CU's (=PS5) to PS4 CU's, RDNA2 (=PS5) FLOPS to PS4 FLOPS etc?
MS confirmed at HotChips that they're using the "mobile variant" of Zen2 aka 4 MB L3 per CCX (=8 MB total), 512 KB L2 per core (=4MB total)
Microsoft described the memory allocation as being GPU-optimized, but I don't think either region in memory is exclusive to either client. It's more a question of how many channels a given part of the address space is striped across, and possibly a difference in the granularity of the striping. The CPU side's interconnect bandwidth seems to be sized so that it cannot exceed the bandwidth of either mode, whereas the GPU can.
Compression is already done in various forms. There's DCC and compressed texture formats. There's a higher priority on random access and speed versus disk compression.
The console compression methods suitable for disk IO work with data rates that are on average <10GB/s, versus memory controllers running in the 200+ GB/s or TB/s on-die. Latency-wise, it's potentially up to milliseconds versus hundreds of nanoseconds. Scaling disk compression to that level is prohibitive in terms of the amount of hardware and overhead. A disk access from the perspective of the primary execution loop is still an intermittent and low-bandwidth operation, and the compression methods are designed to take advantage of the different latency and more linear access to achieve more sustained and greater compression.
Every design has a clock ceiling. If RDNA2 is a common foundation for all these products, it wouldn't be unreasonable to see similar design maximums.
Wasn't the number for SRAM, rather than cache?
To be honest I was relying on this Eurogamer astatement to mean cache, because of the phrase across the entire SoC. Some CPU vendors do call their eDRAM or SRAM as cache.
I'd believe Linux commits over "sources" every day of the week
Azalia as in Intel High Definition Audio?
But is non-cache SRAM ever a substantial amount compared to cache SRAM in an APU/CPU/GPU?
An RDNA CU has 256KB of SRAM in its register file alone. Navi 10's 40 CUs have roughly 10 MB of register file versus a 4MB L2.
Not if you care at all about battery life.
Supposedly the initial Linux-commit with HBMs was just placehoilder or something, and there has since been either Linux-commits or other information of similar nature saying it's GDDR. We'll see soon enough.
My point was that Microsoft chose this architecture while also going for "relatively high" 560GB/s. My theory is that PS5/Navi target lower bandwidth in combination with this rumoured, humongous, Infinity Cache, but it's not present in XSX since Microsoft chose to solve the problem in a different way.
It seems like a sizable investment to overcome a 20% bandwidth deficit, for a GPU that is in many metrics ~20% lower in performance.
There are two chips, Navy Flounder and Sienna Cichlid, one is HBM the other is G6.