That thing called engineering.
No need for snark. Come on, grow up. If you don't have anything tangible to discuss, then save the attitude.
That thing called engineering.
I genuinely mean it.No need for snark. Come on, grow up.
Expecting anything less than what PS5 clocks at doesn't make much sense.
Which also has twice as much power allocated to all things GPU, yes.Perhaps, though we are talking about a part that is twice as large as that.
But you just said it was 275W, not in the 400W range. So which is it?Which also has twice as much power allocated to all things GPU, yes.
I never said PS5 GPU was 200W.But you just said it was 275W, not in the 400W range. So which is it?
There's a non-linear relationship with clocks & voltage.
I think he's implying compared to PS5s GPU that 275W would be double. Which I honestly doubt.But you just said it was 275W, not in the 400W range. So which is it?
There's a non-linear relationship with clocks & voltage.
You have your rights to, and AMD has the prowess to prove everyone wrong (maybe even me).Which I honestly doubt.
Yay.Gotcha, thanks.
I'm still waiting for you to post even some speculation tweet or something to back your words, so far I've seen you post nothing to back your words despite always wording your posts like they're facts
Less than AMD anyway.He does seem quite confident doesn’t he?
Yeah.We’re all gonna be super impressed with RDNA2
Yeah.I hope it’s the former.
It also has a vastly bigger config than anything Navi1x, being 52CU and 320b mem.XSX GPU clocks are lower than the majority of RDNA1 boost clocks though including Navi 14.
It's not Boost-clock for XSX though, but constant aka "baseclock with no boost"XSX GPU clocks are lower than the majority of RDNA1 boost clocks though including Navi 14.
Well in that case it's about 100-150 MHz higher than RDNA1. Isn't exactly ground breaking.It's not Boost-clock for XSX though, but constant aka "baseclock with no boost"
Komachi and an Asian supply chain source seem to be teasing Navi 3X being a multi-die design, splitting in GCD (presumably Graphics Core[?] Die) and MCD (presumably Memory Controller Die?).
That being said, how much die space does that split off? I know memory controllers aren't small, but I can't find any estimates.
It's the pilot SoIC product yes.Komachi and an Asian supply chain source seem to be teasing Navi 3X being a multi-die design, splitting into GCD (presumably Graphics Compute[?] Die) and MCD.
Not that.today's TSV packaging tech
Remember that the % would be bigger for a bigger die as the remaining media bloat would stay at a relatively fixed size - at least in theory. The savings wouldn't be also exactly 45% as you'd need to re-add the SerDes with enough bandwidth to the IO die, which would be significantly wider than what we see in Zen2 to be able to feed enough bandwidth. I don't know how much space that'd be but I imagine at least half the size of the current memory PHYs. Obviously that's still around a 30% die savings for a GPU of that class - probably worth it for cost savings and yields.Navi 10
If we assume the annotations in this Reddit post are accurate, shader arrays and the associated graphics functions occupy ~55%.