AMD Exascale Heterogeneous Processor

[Deleted member 13524]

Last month, AMD published an article in IEEE Micro describing their general idea for an APU package that would go into a mainframe capable of an Exaflop of sustained performance.

The article has this diagram of the supposed package:

The diagram shows 32 Zen cores and a grid of 12*18 graphics CUs, together with 8 stacks of HBM. 12*18 = 216, but that may by purely illustrative.

The article claims "10 TFLOPs or more" of sustained performance.

 

[pjbliverpool]

When can I get one for my desktop?

 

[Infinisearch]

Is there a free version of the article anywhere?

 

[trinibwoy]

So lots of cores and lots of memory? I could've designed that

 

[Deleted member 13524]

When can I get one for my desktop?

If this is developed strictly for HPC, they may cut on the fixed function and graphics-specific units, like TMUs and ROPs.
Hence, despite the huge compute power, this might not be very good for gaming.

But what would be really cool is a chip with half those units for the consumer market. 8 Zen cores, 108 CUs, 4 HBM2 stacks for 16GB plus DDR4. All within a single ~400W chip.

Is there a free version of the article anywhere?

To be honest, the article doesn't have much depth at all (I could understand pretty much everything), so it's not like there's a lot of corporate secrets within it.
I have access to it because of my university's protocol with IEEE, but I probably can't share the PDF freely without authorization. Perhaps @Dave Baumann could do something about it?

 

[lanek]

Last month, AMD published an article in IEEE Micro describing their general idea for an APU package that would go into a mainframe capable of an Exaflop of sustained performance.

The article has this diagram of the supposed package:



The diagram shows 32 Zen cores and a grid of 12*18 graphics CUs, together with 8 stacks of HBM. 12*18 = 216, but that may by purely illustrative.

The article claims "10 TFLOPs or more" of sustained performance.

Strange that it have take so much time to surface...

I see something really interessant in the design of computing server coming with this type of things.

Even for "consumer HPC" market.

 

[Blazkowicz]

Would that be ARMv8 cores instead? I can imagine 32 Zen and uncore(s) taking up a lot of area and power. High core Xeons feel pretty filled up as an example.

Missing from the diagram is the interconnect or even whether there is more than one APU per node.

 

[Alexko]

This is supposed to be an exascale design, so it might be intended for a 7nm process, or something like that. Zen cores (or rather Zen derivatives) wouldn't take up that much space on such a process.

 

[Infinisearch]

To be honest, the article doesn't have much depth at all (I could understand pretty much everything), so it's not like there's a lot of corporate secrets within it.

Were there any tidbits on Zen in it? Thats what I'm interested in

 

[Frenetic Pony]

This is supposed to be an exascale design, so it might be intended for a 7nm process, or something like that. Zen cores (or rather Zen derivatives) wouldn't take up that much space on such a process.

Zen is projected to reach 32 cores on 14nm, assuming same die area and perfect scaling (take that with a grain of salt) 7nm would reach 128 cores. Of course 7nm will probably be 2020 at the earliest, 2021+ more likely. Regardless the paper in question was either lucky timing or an early tipoff that Obama was going to signoff on a "go forth and build an exascale computer" thing: http://www.extremetech.com/extreme/...er-to-build-first-ever-exascale-supercomputer

Getting that contract would be a dream for either Intel or AMD to be a part of. A huge government contract, meaning indefinite budget and delivery date, for bragging rights at the end? Hell yeah.

 

[Alexko]

Projected by whom?

 

[Blazkowicz]

Past AMD announcements only have them use single socket consumers chips in servers, on the x86 market.
ARM is where the unusual things happen, such as a die with 16 cores, massive internal bus, four 10Gbe interfaces etc.

Of course that isn't conclusive in itself.

 

[Frenetic Pony]

Projected by whom?

By... AMD. They've already announced they're working on 32 core AMD Zen products, and that they're working on 14nm node. The above paper is just essentially "hey we could just use a somewhat specialized version of what we're already building to make that thing". Pack 10,000+ of these things into custom mobo setup, interlink them with high ultra high bandwidth/low latency fiber optics, probably run fiber optic interlinks to NAND for storage, shove into non conductive oil for cooling, and you've got yourself an exascale computer. Much easier said than done of course.

 

[Alexko]

Where did AMD say anything about 32-core Zen products?

 

[Deleted member 13524]

Were there any tidbits on Zen in it? Thats what I'm interested in

There is no direct mention of Zen or GCN in the article. I assumed these are Zen cores because the x86 are supposedly going into higher performance chips, but I could be wrong.

 

[Deleted member 2197]

Where did AMD say anything about 32-core Zen products?

It is rumored that the processor side of things will get 32 cores, we think Zen micro-architecture here with eight "Zen" quad-core units. AMD is aiming to release the first engineering sample of this what will be a massive chip by 2016-17.

http://www.guru3d.com/news-story/amd-ehp-processor-(ehp)-has-up-to-32-cpu-cores-and-32gb-memory.html

 

[Alexko]

I don't know where Guru3D got the 2016-2017 time frame. It seems to me that a lot of sites are making up a bunch of crap based on an academic paper that may or may not, at some undetermined point in the future, bear some resemblance to an actual product.

 

[Ryan Smith]

I don't know where Guru3D got the 2016-2017 time frame. It seems to me that a lot of sites are making up a bunch of crap based on an academic paper that may or may not, at some undetermined point in the future, bear some resemblance to an actual product.

The only date I've seen attached to the NSCI is that they want to be done in the next decade. I haven't seen any other official dates mentioned, and the whole plan seems like it's about figuring out what the US government is going to order at the end of this decade to replace Summit & Co in the 2020s.

 

[3dilettante]

I don't know where Guru3D got the 2016-2017 time frame. It seems to me that a lot of sites are making up a bunch of crap based on an academic paper that may or may not, at some undetermined point in the future, bear some resemblance to an actual product.

I think a lot of them are making up a bunch of crap based on one diagram they skimmed for free from the article about an academic paper.
Then a lot more of them are making up a bunch of crap based on the crap made up by the articles that skimmed that out of context image for free from an article about an academic paper.

The paper itself is more of a statement of AMD's "vision" for an APU of undefined CPU architecture (one would think that little detail would be nailed down for a chip taping out next year), with a bunch of references to the various papers AMD has made over the last several years on the topic of interposer network on chip integration, region-based coherence, quick-release consistency, race-free synchronization for the shared-memory architecture used by OpenCL, processor in memory, heterogenous power management, and research into software-based error detection and correction in lieu of reliable hardware.
To note, these are call-backs to these papers. The paper itself is rather meatless.
Each of these are appended with a call for more research in order to make something of them.

 

[Frenetic Pony]

To note, these are call-backs to these papers. The paper itself is rather meatless.
Each of these are appended with a call for more research in order to make something of them.

Like I said, this just looks like an advertisement for AMD to be a part of the US Government's new exascale computer project, rather than any actual project. "Hey look what we could do if we had money!" and the title of the paper says EXASCALE COMPUTING in nice big letters so the government wonks can understand it. Considering the amount of press this got, I'd say it's a pretty cheap marketing success for AMD so far.